Question Zen4c vs E core Die area.

[eek2121]

Density optimised Zen 4. The chiplet itself is less than 10% larger and it has double the core count vs the standard Zen 4 CCD. That is split into 2 CCXs each with 16MB of L3 so per core L3 is halved.

…and a 50-60% lower clockspeed.

This means that unless clocks improve, gracemont and Zen 4c should be pretty close in terms of performance.

It will be interesting to see comparisons. If Bergamo weren’t guaranteed to cost an arm and 3 legs I would be tempted to grab one for review purposes.

 

[Markfw]

…and a 50-60% lower clockspeed.

This means that unless clocks improve, gracemont and Zen 4c should be pretty close in terms of performance.

It will be interesting to see comparisons. If Bergamo weren’t guaranteed to cost an arm and 3 legs I would be tempted to grab one for review purposes.

2.84 ghz for 256 threads ? Thats pretty damn good, I don't see how that is 50-60% slower. My 9654 only runs 2400 with 192 threads on some apps. 2750 is the highest I have seen. Gracemont won't be close.

 

[igor_kavinski]

Yep, I gladly and wholeheartedly agree with you. The trouble is, that I do not have a machine at my disposal that would allow me that kind of thorough testing.

Sent you a PM.

 

[moinmoin]

…and a 50-60% lower clockspeed.

Lower peak clockspeed you mean.

The whole point about these "cloud" specific cores is to have a more predictable sustained clockspeed. That one may well be higher than what's possible on current chips by both AMD and Intel.

 

[Abwx]

All this tells me is that you have no idea what that term is. To give the simplest possible example, if you have two identical transistors instead of one, that term would ~double. So no, it is not in any way redundant, nor scales with frequency. It's a constant for a given design and workload.

There s much confusion in your understanding of things.

You always have at least two transistors since they are always connected as complementary pairs, and such a basic stage FI is called an inverting gate or rather stage.

The total capacitance of this stage is twice the one of a transistor by the definition, simply the dynamic capacitance is the the sum of gate/source and gate/drain capacitances, this total capacitance is charged and discharged every cycle by the previous stage that drive said stage.

The energy required to charge this capacitance C is C.V^2, and as much energy is required to discharge it since the reactive power is provided by the power supply, as such a CPU can be considered as a giant capacitor whose impedance is 1/2.pi.F.C, C being here the total capacitance of the CPU.

There s another capacitance of way lower value that is connected from each transistor drain to their gate, and its called the Miller capacitance, it require very few energy to charge and discharge but has a dreadfull influence for the transistor switching speed.

Since it s connected from output to input of the transistor and that the transistor work as an inverter with big voltage gain this Miller capacitance C create a negative feedback action and relatively to the transistor speed it act as if its effective value is C.G, G being the voltage gain of the transistor, so the apparent capacitance is the effective capacitance time the transistor gain.

With Planar transistor this capacitance is very low but with finfets its value has lot of influence for the transistor speed, moreover due to the fact that finfets have much higher gain than planar transistors, hence even if the dynamic capacitance can be easily charged/discharged the transistor will be slowed by the negative feedback from output to input.

Hope it did help to understand better the capacitive effects at work in a transistor, there s other parameter that act as well but for the time it s enough to understand these ones.

 

[Tuna-Fish]

With all IO being equal, they can sell a SMT core as 2 vCPUs vs just 1 CPU if disabled

The norm in the market for CPUs that have SMT is to sell as 2 vCPUs, but allow the customer to disable one of them if they want to.

 

[Exist50]

There s much confusion in your understanding of things.

You always have at least two transistors since they are always connected as complementary pairs, and such a basic stage FI is called an inverting gate or rather stage.

The total capacitance of this stage is twice the one of a transistor by the definition, simply the dynamic capacitance is the the sum of gate/source and gate/drain capacitances, this total capacitance is charged and discharged every cycle by the previous stage that drive said stage.

The energy required to charge this capacitance C is C.V^2, and as much energy is required to discharge it since the reactive power is provided by the power supply, as such a CPU can be considered as a giant capacitor whose impedance is 1/2.pi.F.C, C being here the total capacitance of the CPU.

There s another capacitance of way lower value that is connected from each transistor drain to their gate, and its called the Miller capacitance, it require very few energy to charge and discharge but has a dreadfull influence for the transistor switching speed.

Since it s connected from output to input of the transistor and that the transistor work as an inverter with big voltage gain this Miller capacitance C create a negative feedback action and relatively to the transistor speed it act as if its effective value is C.G, G being the voltage gain of the transistor, so the apparent capacitance is the effective capacitance time the transistor gain.

With Planar transistor this capacitance is very low but with finfets its value has lot of influence for the transistor speed, moreover due to the fact that finfets have much higher gain than planar transistors, hence even if the dynamic capacitance can be easily charged/discharged the transistor will be slowed by the negative feedback from output to input.

Hope it did help to understand better the capacitive effects at work in a transistor, there s other parameter that act as well but for the time it s enough to understand these ones.

As I'm trying to explain to you, different designs have different numbers of transistor, different transistor characteristics, and different VF curves. Not sure why this is hard to grasp.

 

[nicalandia]

…and a 50-60% lower clockspeed.

This means that unless clocks improve, gracemont and Zen 4c should be pretty close in terms of performance.

You are Way Off. 2P Bergamo is trashing 4P Sapphire Rapids at less than 600 total watt at 100% Load in SPEC. Old Skylake Xeons that can do 4P and 8P dont even come close. You are putting too much faith on those little cores.

 

[Abwx]

As I'm trying to explain to you, different designs have different numbers of transistor, different transistor characteristics, and different VF curves. Not sure why this is hard to grasp.

When i said that power frequency curves have an exponent between 2.2 and 2.8, what does it mean for you..?..

Apparently nothing since it s you that are in difficulty to grasp things, a curve with a 2.2 exponent is by the definition different from a curve with a 2.6 exponent when it comes to frequency voltage curve, it s the slope of the voltage frequency curve that move the exponent at a different value than the ideal value of 2 for ideal mosfets.

So a 2.6 exponent means a steeper slope of the voltage frequency curve than a 2.2 exponent, that s basic math at play here, but of course you are supposed to know all the implicit realations.

FI for an ideal mosfet its non normalized switching frequency capability is F= V^0.5, if it s not an ideal mosfet then this exponent is greater than 0.5, say 0.7, in wich case the power/frequency curve will be of the form P = F^2.4

 

[soresu]

View attachment 81798

How do they manage to add another CPU package to go from 128 -> 256C with only <41% increase in 100% Load wattage?

Are the 2S IO/platform power draw overheads that significant? 😱

 

[nicalandia]

How do they manage to add another CPU package to go from 128 -> 256C with only <41% increase in 100% Load wattage?

Are the 2S IO/platform power draw overheads that significant? 😱

I don't know, but AMD did some Voodoo Magic when 2P Bergamo at 600 Watts it's Beating 4P Top of the line 8490H in performance(1280 Watts).

 

[A///]

What do you know? It actually might be: https://www.tomshardware.com/news/i...ew-chinas-exclusive-black-edition-gaming-chip

It's a lot of effort and binning to go through if the availability is good, but again it's only china. I don't care enough to look into it but it's interesting to see if it's meant as a test bed processor because how prolific gaming is in china wihth certain age demographics.

 

[soresu]

I don't know, but AMD did some Voodoo Magic when 2P Bergamo at 600 Watts it's Beating 4P Top of the line 8490H in performance(1280 Watts).

Lol ye - >2x the cores at <50% the power consumption for >2.6x SpecPower (perf/watt bench?)😂

If Bergamo isn't already selling like hotcakes they will after these benches.

Did I see something about a possible 4S platform for future Zen servers?

Or was that MIxxx perhaps.....

I'd be interested to see how well the 2S 256C configuration does with offline ray/path traced rendering tasks ala Arnold/Renderman/Cycles.

Lol - a single one of them is probably easily exceeding the total perf of the render farm they used for LOTR Return of the King 😅

 

[nicalandia]

Lol ye - >2x the cores at <50% the power consumption for >2.6x SpecPower (perf/watt bench?)😂

If Bergamo isn't already selling like hotcakes they will after these benches.

Did I see something about a possible 4S platform for future Zen servers?

Or was that MIxxx perhaps.....

I'd be interested to see how well the 2S 256C configuration does with offline ray/path traced rendering tasks ala Arnold/Renderman/Cycles.

Lol - a single one of them is probably easily exceeding the total perf of the render farm they used for LOTR Return of the King 😅

Question - 2S AMD EPYC 9754 vs 4P Intel Xeon Platinum 8490H Performance/Power

OS: SUSE Linux Enterprise Server 15 SP4 AMD EPYC 9754 2P(256C/512T) Active Package Power: 800 Watts at 100% Load SPEC2017 Integer Rate Result: 1950 https://www.spec.org/cpu2017/results/res2023q2/cpu2017-20230522-36617.html...

forums.anandtech.com

For those that think Sierra Forest stand a chance.

 

[DrMrLordX]

There is no product from Intel out there with nothing but e-cores, so how can we compare ????

@Exist50 mentioned Alder Lake-N, though it is gimped by single-channel RAM.

For those that think Sierra Forest stand a chance.

Let's let the product launch or not and then judge accordingly. Bergamo does present stiff competition. I'm not sure we can exactly extrapolate Sierra Forest/Crestmont performance from Sapphire Rapids which is sort of a cursed product. It does look bad for Intel that we'll have to wait for Q2 2024 to even find out if Intel can compete with Bergamo.

 

[Henry swagger]

Question - 2S AMD EPYC 9754 vs 4P Intel Xeon Platinum 8490H Performance/Power

OS: SUSE Linux Enterprise Server 15 SP4 AMD EPYC 9754 2P(256C/512T) Active Package Power: 800 Watts at 100% Load SPEC2017 Integer Rate Result: 1950 https://www.spec.org/cpu2017/results/res2023q2/cpu2017-20230522-36617.html...

forums.anandtech.com

For those that think Sierra Forest stand a chance.

Amd is not paying you.. why you so excited

 

[coercitiv]

Amd is not paying you.. why you so excited

He saw your 7Ghz posts and thought this was a cheerleading competition.

 

[Exist50]

For those that think Sierra Forest stand a chance.

So just to be clear, you think a full node shrink, different SoC design, and several times the core count will have no impact on its competitiveness? What, exactly, do you think makes Bergamo good? Magic? Or have you just abandoned all common sense by this point?

 

[coercitiv]

So just to be clear, you think a full node shrink, different SoC design, and several times the core count will have no impact on its competitiveness?

Do we know if Sierra Forest is still using the mesh interconnect? I'm curious to know whether they'll still use some type of E-core module or this was done solely to accommodate E-cores on the consumer ring bus.

 

[Exist50]

Do we know if Sierra Forest is still using the mesh interconnect? I'm curious to know whether they'll still use some type of E-core module or this was done solely to accommodate E-cores on the consumer ring bus.

Sierra Forest should be pretty much the same SoC as Granite Rapids, just substituting a Redwood Cove core for a Crestmont (?) module. So yes, that looks to mean the mesh, though fewer die to die hops should help vs SPR.

 

[Henry swagger]

He saw your 7Ghz posts and thought this was a cheerleading competition.

My prediction will be true 😏

 

[igor_kavinski]

My prediction will be true 😏

Intel predicted 10 GHz too.

The future of Intel's manufacturing processes

www.anandtech.com

Whatever happened to that?

 

[soresu]

Intel predicted 10 GHz too.

Gawd no, don't remind us! 🔥🔥🔥💥💥💥

What was it called, Tejarus or something?

 

[soresu]

Isn't it a thing that some transistors can do over 10 ghz easy, but actually feeding them with data fast enough becomes a problem (latency wise) without optical IO due to the fundamental speed limit?

Maybe I'm just misremembering an article.... 👴

Edit: Just calculating (unless my math is way off) at 10 Ghz a photon could have only travelled 29.9 mm per cycle - that still sounds viable, but going higher than that (especially over 100 Ghz) might introduce serious latency problems if the data has to traverse any significant distance across the die.

 

[nicalandia]

So just to be clear, you think a full node shrink, different SoC design, and several times the core count will have no impact on its competitiveness? What, exactly, do you think makes Bergamo good? Magic? Or have you just abandoned all common sense by this point?

Unlike most benchmarks SPEC 2017 Scales linearly with sockets so in this case, I fully expect a 4P Sapphire Rapids with 240C/480T to outperform a Sierra Forrest in Integer performance(SPECInt2017) and specially in FPU performance. Not withstanding Power consumption of course as Sierra Forest will be more efficient.