Question Zen4c vs E core Die area.

[Tuna-Fish]

Isn't it a thing that some transistors can do over 10 ghz easy, but actually feeding them with data fast enough becomes a problem (latency wise) without optical IO due to the fundamental speed limit?

A single transistor switching as fast as it can on modern processes can do something like 100-200GHz.

However, you cannot build a processor out of a single transistor. You build long chains of logic, and the clock rate of the CPU is the rate that the entire chain switches -- that is, clock signal fires, latches change their outpus for first transistors in the chain, which then switch. These transistors feed their outputs as inputs to other transistors (suffering wire delays on the way), which switch, etc, until the signals finally reach the inputs of latches. The maximum clock rate of a CPU depends on how fast the longest, slowest chain will reliably get all their work done and the signals into latches.

The "clock rates" of individual transistors need to greatly exceed the clock rate of the CPU as whole, if you intend to do anything useful.

 

[Abwx]

Zen 4 added a lot of transistors for seemingly no reason. One theory was that they where added to allow to drive the high frequency achieved. According to that Zen 4c removed those again and as such is closer to the transistor count of Zen 3 and able to realize the area saving from going to the newer node. Going by that Zen 4c likely has a lower hard limit akin to the Zen gens until Zen 3 where it just wasn't possible to exceed a specific frequency no matter the power used.

Putting more transistors can théorically increase max frequency by 30% or so, and somewhat less in practice, removing the excess transistors wont decrease efficency at average frequency, it should be possible to hit 4.5Ghz with equivalent efficency than the boosted version at this same frequency.

A single transistor switching as fast as it can on modern processes can do something like 100-200GHz.

That s the transition frequency of the transistor , the frequency at wich as much energy is required to drive the transistor than to get the same amount of energy at its output, to say it more simply this is its unity gain frequency.

This apply only for a sine of said frequency, to have an usable clock signal harmonics of 20th order at least are required to have a square wave shape, that s why CPUs are limted to 5Ghz or so, at this clock the higher frequency sines in a square wave signal exceed 100GHz.

 

[Joe NYC]

Even using Zen4c, it seems unlikely they'd go as far as 16c for a consumer product. Unless that's the smallest they could go.

I don't think it will happen with Zen4c but Zen5c will be on N3, and will be a native 16 core CCD, not 2x8CCX.

I think AMD will try to look for places to reuse it.

 

[Exist50]

I don't think it will happen with Zen4c but Zen5c will be on N3, and will be a native 16 core CCD, not 2x8CCX.

I think AMD will try to look for places to reuse it.

It would be interesting to see how they would implement a 16c CCX. They use a ring bus now, but like Intel's seeing, scaling that to 16 endpoints would be somewhat challenging. Not impossible, just challenging. Might have to go for some sort of hierarchical fabric.

 

[Joe NYC]

It would be interesting to see how they would implement a 16c CCX. They use a ring bus now, but like Intel's seeing, scaling that to 16 endpoints would be somewhat challenging. Not impossible, just challenging. Might have to go for some sort of hierarchical fabric.

There was a video by Jim from AdoredTV that described some sort of elevator ring / mesh. Which has some shortcuts across the ring. He said it is coming to Zen 5.

8 core CCD is not exactly hurting with the current ring bus, so the real objective, IMO, is for the 16 core CCDs.

And regarding the 16 core CCDs, Zen 5 dense will according to other leaks, lead the Zen 5 server line up, and will be on N3.

So it seems like all these dots are connecting quite well.

 

[soresu]

And regarding the 16 core CCDs, Zen 5 dense

How does Z5 dense differ from Z5c?

 

[Joe NYC]

How does Z5 dense differ from Z5c?

It is the same think. I think AMD just renamed the former name "dense" to the nonsensical marketing phrase "cloud" native.

 

[Hitman928]

Putting more transistors can théorically increase max frequency by 30% or so, and somewhat less in practice, removing the excess transistors wont decrease efficency at average frequency, it should be possible to hit 4.5Ghz with equivalent efficency than the boosted version at this same frequency.




That s the transition frequency of the transistor , the frequency at wich as much energy is required to drive the transistor than to get the same amount of energy at its output, to say it more simply this is its unity gain frequency.

This apply only for a sine of said frequency, to have an usable clock signal harmonics of 20th order at least are required to have a square wave shape, that s why CPUs are limted to 5Ghz or so, at this clock the higher frequency sines in a square wave signal exceed 100GHz.

Transition frequency (ft) is unity current gain. CMOS processes/designers typically look at the maximum frequency (fmax) spec when comparing transistors and modern transistors can oscillate at hundreds of GHz.

Square waves only use the odd harmonics and modern transistors on their own are fast enough to give you really good square waves; the devices being able to inherently oscillate with a square wave fast enough isn't the limiting factor in getting to 10 GHz as Intel found out with Tejas.

 

[Hitman928]

There s much confusion in your understanding of things.

You always have at least two transistors since they are always connected as complementary pairs, and such a basic stage FI is called an inverting gate or rather stage.

The total capacitance of this stage is twice the one of a transistor by the definition, simply the dynamic capacitance is the the sum of gate/source and gate/drain capacitances, this total capacitance is charged and discharged every cycle by the previous stage that drive said stage.

The energy required to charge this capacitance C is C.V^2, and as much energy is required to discharge it since the reactive power is provided by the power supply, as such a CPU can be considered as a giant capacitor whose impedance is 1/2.pi.F.C, C being here the total capacitance of the CPU.

There s another capacitance of way lower value that is connected from each transistor drain to their gate, and its called the Miller capacitance, it require very few energy to charge and discharge but has a dreadfull influence for the transistor switching speed.

Since it s connected from output to input of the transistor and that the transistor work as an inverter with big voltage gain this Miller capacitance C create a negative feedback action and relatively to the transistor speed it act as if its effective value is C.G, G being the voltage gain of the transistor, so the apparent capacitance is the effective capacitance time the transistor gain.

With Planar transistor this capacitance is very low but with finfets its value has lot of influence for the transistor speed, moreover due to the fact that finfets have much higher gain than planar transistors, hence even if the dynamic capacitance can be easily charged/discharged the transistor will be slowed by the negative feedback from output to input.

Hope it did help to understand better the capacitive effects at work in a transistor, there s other parameter that act as well but for the time it s enough to understand these ones.

The gate to drain capacitance is the base of the miller capacitance. The miller effect on this capacitor is that there is a voltage dependence for this cap, thus the miller capacitance is the gate to drain capacitor with the applied miller effect. In digital circuits, since you are consistently driving the same voltage range, it can be accurately modeled as a constant effect added to the load of the driving gate. Even with this effect, the gate to source capacitance of the following stage is typically the dominant factor in the load that each gate has to drive. I don't work in FinFET technology so the miller effect may have an increased effect there though I would imagine it would be primarily due to the 3D nature of the gate creating additional gate to drain capacitance that you don't have in planar transistors.

 

[Abwx]

Transition frequency (ft) is unity current gain. CMOS processes/designers typically look at the maximum frequency (fmax) spec when comparing transistors and modern transistors can oscillate at hundreds of GHz.

Square waves only use the odd harmonics and modern transistors on their own are fast enough to give you really good square waves; the devices being able to inherently oscillate with a square wave fast enough isn't the limiting factor in getting to 10 GHz as Intel found out with Tejas.

Unity current gain is specificaly for bipolar transistors beta, for fets its the energy required to charge the input capacitances, so as much current is required to drive the input than what will be switched on by the fet drain/source junction, otherwise a fet current gain is almost unlimited since its input impedance is typicaly 10^12 ohms.

As for square wave i m aware that there s only odd harmonics, but for a 5GHz clock signals to be usable it require high orders harmonics to be present, it s these higher order harmonics that make the front end signal rising sharply.

If there was only the fundamentaland say the third harmonic then the signal slew rate would be very low and you couldnt have a functional digital circuitry clocked at the fundamental frequency.

 

[Abwx]

The gate to drain capacitance is the base of the miller capacitance. The miller effect on this capacitor is that there is a voltage dependence for this cap, thus the miller capacitance is the gate to drain capacitor with the applied miller effect. In digital circuits, since you are consistently driving the same voltage range, it can be accurately modeled as a constant effect added to the load of the driving gate. Even with this effect, the gate to source capacitance of the following stage is typically the dominant factor in the load that each gate has to drive. I don't work in FinFET technology so the miller effect may have an increased effect there though I would imagine it would be primarily due to the 3D nature of the gate creating additional gate to drain capacitance that you don't have in planar transistors.

I' m also aware of what is the miller capacitance, i gave an explanation of the thing a few days ago in this forum.

The miller capacitance has a big effect even if energy wise the gate source capacitance is by far the most power consuming one, but as far as speed is a concern the miller capacitance is multiplied by the transistor gain when we talk of the switching speed capability.

It wasnt a big concern for planar transistors but with finfets it must be considered because of the much augmented gate surface that increase this capacitance, it s this augmented gate surface that allow finfets to have much better transconductance than planar fets, the downside is the big increase of miller capacitance and it has to be accounted in design, usually this is tamed down by cascoding two fets as a single device.

Edit : The miller capacitance negative feedback effect reduce greatly the transistor gain at the higher frequencies, so the higher order harmonics amplitude is much reduced, as a consequence the signal slew rate is also greatly reduced, wich limit the max clock of the circuitry.

 

[Hitman928]

Unity current gain is specificaly for bipolar transistors beta, for fets its the energy required to charge the input capacitances, so as much current is required to drive the input than what will be switched on by the fet drain/source junction, otherwise a fet current gain is almost unlimited since its input impedance is typicaly 10^12 ohms.

No, this is just wrong. Transition frequency is measured the same way whether it is a FET or a BJT and is defined as the unity current gain and it is absolutely not almost unlimited for a FET. A FET's input impedance is only considered high impedance at low frequencies. At millimeter wave frequencies, it's input impedance changes significantly.

As for square wave i m aware that there s only odd harmonics, byr for a 5GHz clock signals it require to be usable it require high orders harmonics to be present, it s these higher order harmonics that make the fron end riding sharply.

If there was only the fundamentaland say the third harmonic then the signal slew rate would be very low and you couldnt have a functional digital circuitry clocked at the fundamental frequency.

Third harmonic of a 5 GHz signal is only 15 GHz. If you wanted the 41st harmonic, that is 205 GHz which is still within range of modern transistors. You also don't need a perfect square wave for CMOS design and you never get a perfect square wave (or even really near perfect) with high frequency designs. But again, passing a square wave intrinsically through the transistor is not the limiting factor.

 

[Hitman928]

I' m also aware of what is the miller capacitance, i gave an explanation of the thing a few days ago in this forum.

The miller capacitance has a big effect even if energy wise the gate source capacitance is by far the most power consuming one, but as far as speed is a concern the miller capacitance is multiplied by the transistor gain when we talk of the switching speed capability.

It wasnt a big concern for planar transistors but with finfets it must be considered because of the much augmented gate surface that increase this capacitance, it s this augmented gate surface that allow finfets to have much better transconductance than planar fets, the downside is the big increase of miller capacitance and it has to be accounted in design, usually this is tamed down by cascoding two fets as a single device.

Edit : The miller capacitance negative feedback effect reduce greatly the transistor gain at the higher frequencies, so the higher order harmonics amplitude is much reduced, as a consequence the signal slew rate is also greatly reduced, wich limit the max clock of the circuitry.

Cascoding is not connecting two FETs as a single device, it is connecting a common gate configured amplifier (FET) to the output of a common source amplifier (FET). You can model them together as a single amplifier, but they are not treated as a single device. This is an analog technique and is never done in digital circuits.

I can believe that the miller effect has a greater effect on FinFETs, but they also have higher transition frequencies and maximum frequencies so we’re back again to that not being a limiting factor.

 

[Abwx]

No, this is just wrong. Transition frequency is measured the same way whether it is a FET or a BJT and is defined as the unity current gain and it is absolutely not almost unlimited for a FET. A FET's input impedance is only considered high impedance at low frequencies. At millimeter wave frequencies, it's input impedance changes significantly.

That s what i said, eitheryou just didnt understand my point or you dont know how these transistors work.

In a bipolar transistor the drive current is absorbed mainly by the transistor base and flow through the emitter, at unity gain the base current is as high as the collector/emitter current.
For a fet i said that it has almost unlimited input impedance, so no current flow through the gate, at unity gain all the input current is absorbed by the input capacitance, so at the end the result is the same, the drive current current is equal to the output current.

 

[Abwx]

Cascoding is not connecting two FETs as a single device, it is connecting a common gate configured amplifier (FET) to the output of a common source amplifier (FET). You can model them together as a single amplifier, but they are not treated as a single device. This is an analog technique and is never done in digital circuits.

I can believe that the miller effect has a greater effect on FinFETs, but they also have higher transition frequencies and maximum frequencies so we’re back again to that not being a limiting factor.

One more time you didnt get the point, i was talking of the functionality of the arrangement.

Cascoding two transistors result as a same device functionaly wise, there s an input, either the gate or the base of the first transistor, and there s an inverting output, either the drain or the collector of the second transistor.

The cascode arrangement work as a single transitor set apart that the output is insulated from the input, the miller capacitance of the output device is, electricaly speaking, shorted to the ground while the miller capacitance of the first device see no voltage variation at its ends, so it is neutered.

As for finfets designers have to take account of the miller capacitance because not only it is of higher value than in planar fet transistors but also because finfets have much higher transconductance, or said more simply, more amplification, and higher Ft wont change nothing if this capacitance is not neutered, because the higher the transistor gain the higher the apparent capacitance.

The product of this capacitance by the transistor gain yield the apparent capacitance seen by the driving stage speed wise but not energy wise, the device get slower because of the frequency dependent negative feedback from output to input, and as said the higher the transistor gain the higher the negative feedback ratio, but also the higher the frequency the lowest the impedance presented by this capacitance, and hence the higher the negative feedback as well, that s a basic of electronics theories and design.

 

[Hitman928]

One more time you didnt get the point, i was talking of the functionality of the arrangement.

Cascoding two transistors result as a same device functionaly wise, there s an input, either the gate or the base of the first transistor, and there s an inverting output, either the drain or the collector of the second transistor.

The cascode arrangement work as a single transitor set apart that the output is insulated from the input, the miller capacitance of the output device is, electricaly speaking, shorted to the ground while the miller capacitance of the first device see no voltage variation at its ends, so it is neutered.

As for finfets designers have to take account of the miller capacitance because not only it is of higher value than in planar fet transistors but also because finfets have much higher transconductance, or said more simply, more amplification, and higher Ft wont change nothing if this capacitance is not neutered, because the higher the transistor gain the higher the apparent capacitance.

The product of this capacitance by the transistor gain yield the apparent capacitance seen by the driving stage speed wise but not energy wise, the device get slower because of the frequency dependent negative feedback from output to input, and as said the higher the transistor gain the higher the negative feedback ratio, but also the higher the frequency the lowest the impedance presented by this capacitance, and hence the higher the negative feedback as well, that s a basic of electronics theories and design.

If you are going to engage in a technical discussion you need to use technical terms correctly and be clear about what you are saying. Your claim that a cascode amplifier works as a single transistor is ridiculous and the miller cap of the output device is not shorted to the ground (which would imply both the drain of the output transistor and its gate are grounded) but the gate of the output transistor is an AC (not DC) ground so there can't be any AC feedback effect. You also tend to jump around on topics because this really has nothing to do with a discussion on digital circuits.

Higher transconductance improves Ft. The gate to drain cap of a FET is also included in the ft calculation/measurement (it's in the denominator), so actually a higher ft does show that the increased capacitance isn't enough to offset the increased transconductance of the device. Your argument that transistors aren't inherently fast enough to pass a quality square wave over ~5 GHz is ridiculous. You do know there are digital circuits out there that are well above 5 GHz, right?

 

[Abwx]

If you are going to engage in a technical discussion you need to use technical terms correctly and be clear about what you are saying. Your claim that a cascode amplifier works as a single transistor is ridiculous and the miller cap of the output device is not shorted to the ground (which would imply both the drain of the output transistor and its gate are grounded) but the gate of the output transistor is an AC (not DC) ground so there can't be any AC feedback effect. You also tend to jump around on topics because this really has nothing to do with a discussion on digital circuits.

Higher transconductance improves Ft. The gate to drain cap of a FET is also included in the ft calculation/measurement (it's in the denominator), so actually a higher ft does show that the increased capacitance isn't enough to offset the increased transconductance of the device. Your argument that transistors aren't inherently fast enough to pass a quality square wave over ~5 GHz is ridiculous. You do know there are digital circuits out there that are well above 5 GHz, right?

A higher transconductance doesnt forcibly improve Ft, it improve the gain within the frequency range wich is immune to miller effect but at the higher frequencies of interest the more the gain the more the capability of the miller cap to tame down the gain, what is gained by the better transconductance is lost because the product of the gain by the miller cap increase as well, that is, the negative feedback ratio increase with the increased gain.

If we take two N fets the driven fet has its drain connected to the source of the output fet while the gate of the latter is connected to the positive rail, the output device is always on, it s the input device that is switched on and off, it s in serial with the output device.

Since the output device has its gate connected to the positive rail it is shorted to ground AC wise, so its miller cap is also AC shorted to ground.

About switching speed if we take a 5GHz square wave, or a 0.2 ns peridodic signal, the fundamental is a 5GHz sine, it take 0.05 ns for this sine to reach full amplitude, by the same token the third harmonic is at 15GHz, and it take anout 0.016 ns to reach full amplitude.

If the signal is limited to those two harmonics then cross conduction will occur during 0.01ns, that is, 20% of the duration of the first half period, during wich both transistors of a complementary pair will be conducting simultaneaously, and the same when the signal switch to the other direction, that s just too slow and during the cross conduction current will rise sharply and one, or both, of the transistors will be destroyed by excessive current, so harmonics of way higher order are necessary to have fast enough rising and falling hedges.

To digress somewhat, with bipolar transistors of a same model there s manufacturing variations, and the lower the gain the higher the bandwith of the device, that seem counter intuitive at first but logical when we look at the gain x miller cap product, and when we look at different devices of same current capabilities thoses wich are 3-5GHz capables have way lower gain in a 10 ratio at least than 100-300Mhz only devices...

 

[Thunder 57]

Could we, you know, maybe stay on topic?

 

[Schmide]

but the gate of the output transistor is an AC (not DC) ground so there can't be any AC feedback effect.

does AC stand for Alternating Current or something else?

 

[Hitman928]

does AC stand for Alternating Current or something else?

Alternating current.

 

[Schmide]

Alternating current.

I don't know all the ins and outs of chips, but I doubt there is AC current in there.

 

[Hitman928]

I don't know all the ins and outs of chips, but I doubt there is AC current in there.

Not to get too into, but like I said, cascode amplifiers are analog (AC) designs and I don’t know why it was brought up when discussing digital circuits.

 

[Hitman928]

Could we, you know, maybe stay on topic?

Agreed, I won’t contribute any more about it since it’s just a bunch of tangents anyway.

 

[Abwx]

I don't know all the ins and outs of chips, but I doubt there is AC current in there.

That s not a matter of AC current as such, that s for the understanding more than anything else, it s a matter of dv/dt, and although it sound counter intuitive for most people digital circuitries are built using purely analog devices...

Not to get too into, but like I said, cascode amplifiers are analog (AC) designs and I don’t know why it was brought up when discussing digital circuits.

I wont insist much, but if one want a fast logical inverter using usually two complementary fets then speed can be increased by cascoding each of the complementary devices, that s not only a matter of purely analog circuitries like operational amplifiers, it extend to digital dedicated circuitries.

 

[FangBLade]

Amd is not paying you.. why you so excited

You are excited about every Intel move, does that mean they pay you?

edit: BTW I've already written this once, and I'll write it again - I like your trolling style xD. You're aware that we all know you're trolling, yet you continue without changing your tone, staying true to that role.