ZEN ES Benchmark from french hardware Magazine

[Abwx]

The credibility of this magazine is very low therefore, they are just trolling around and the people buy it.

Surely that the guy who is behind CPUZ and Memtest86+ (that he designed using Memtest86 as basis) is someone who s credibility can be questionned by whoever post on any forum, that being said he knows insiders within both Intel and AMD and it is clearly stated on the articles of the last edition...

 

[zinfamous]

do you know more then lisa?

https://youtu.be/4DEfj2MRLtA?t=27m30s

"today i can tell you our horizon processors at launch will have base clock speeds of 3.4 ghz or higher"

That comment doesn't dispute what Flan3r is saying. Lisa here could actually be saying that initial launch will involve their top-binned Ryzen chips that bottom out at 3.4ghz, but they can still release 8C chips that bottom out as low as 3ghz later, I imagine.

 

[AtenRa]

That comment doesn't dispute what Flan3r is saying. Lisa here could actually be saying that initial launch will involve their top-binned Ryzen chips that bottom out at 3.4ghz, but they can still release 8C chips that bottom out as low as 3ghz later, I imagine.

At 95W TDP base clocks will be 3.4GHz and higher, of course they could release an 8C 16T at 35W TDP later on at lower base clocks but at 95W TDP the 3.4GHz will be the lower base frequency. That is what i get from them.

 

[ecogen]

That comment doesn't dispute what Flan3r is saying. Lisa here could actually be saying that initial launch will involve their top-binned Ryzen chips that bottom out at 3.4ghz, but they can still release 8C chips that bottom out as low as 3ghz later, I imagine.

So they will release 8C chips, after the initial launch that will be running at base clocks lower than even the old ES that was used in this review?

 

[.vodka]

Think about it. The twitter message is dated from 6th December, when the AMD graphics licensing deal was lifted and floated around in many news. So this is just based on the licensing deal, means there is no confirmation for an Intel chip with AMD graphics. You may be wasn't aware that Intel had previously such a deal with Nvidia, do you see Intel CPUs with Nvidia graphics build in somewhere? The credibility of this magazine is very low therefore, they are just trolling around and the people buy it. They also denied the 5 Ghz air message, it was just another trolling.

I am aware of the nV-Intel deal. I am also aware Intel has moved away from nV and is now licensing AMD's graphics, whether to continue improving their own or outright start using AMD's. RTG is now a somewhat separate entity from AMD, they're marketed without AMD in the name now. (They should just bring back ATI while we're at it...) They're free to do whatever they want with their IP as long as it brings them some $$$. Remember this? Therefore I don't discard AMD partnering up with nV to sell Ryzen + NV GPU combos sometime in the future, at least until Vega comes.

Where have they denied the 5GHz message? You don't publish a few thousand magazines and an online version of it, with the binary string, only to deny it later. That's nonsense.

Besides, we don't know the specifics of the 5GHz on air thing. It could mean KBL like stability at 5GHz on air, or just a 5GHz validation, or single core turbo eating up all 95W TDP at 5GHz, etc. If anything it assures that Zen isn't clock capped.

On the credibility part..

Surely that the guy who is behind CPUZ and Memtest86+ (that he designed using Memtest86 as basis) is someone who s credibility can be questionned by whoever post on any forum, that being said he knows insiders within both Intel and AMD and it is clearly stated on the articles of the last edition...

This, and this a while ago.

Yeah. They're more credible than wccfcrap and whatever other clickbait crap you get to find on the internet. You'd better start taking what they say with a little more than skepticism. CES is only a week away, we'll see what's up.

 

[frozentundra123456]

Yeah I see where you got that, the 3.4 ghz or higher obviously meant 3.4ghz or lower. Wasn't this binary obviously fake by the way? What happened with that?

The statement is ambiguous. No need to get sarcastic and attack someone personally. It does not say "all Zen cpus will have 3.4ghz base clock or higher". One could interpret it in that way, but it certainly does not say that specifically. My interpretation is that there will be one sku with a 3.4 ghz base clock or higher if they can get the clockspeeds up. There may, however, be cheaper skus with lower clockspeeds. I dont think they would promote the product by listing the clockspeed of a mid-range chip. And we have seen no leaks of a stock Zen running faster than 3.4ghz unless overclocked. Now if there is only one model at launch, it obviously *will* have 3.4ghz or higher base, and a price to match. I would also expect cheaper, lower clocked models as the line expands.

 

[ecogen]

The statement is ambiguous. No need to get sarcastic and attack someone personally. It does not say "all Zen cpus will have 3.4ghz base clock or higher". One could interpret it in that way, but it certainly does not say that specifically. My interpretation is that there will be one sku with a 3.4 ghz base clock or higher if they can get the clockspeeds up. There may, however, be cheaper skus with lower clockspeeds. I dont think they would promote the product by listing the clockspeed of a mid-range chip. And we have seen no leaks of a stock Zen running faster than 3.4ghz unless overclocked. Now if there is only one model at launch, it obviously *will* have 3.4ghz or higher base, and a price to match. I would also expect cheaper, lower clocked models as the line expands.

I was only being sarcastic because of the person I was replying to, who seems to want to immediately discredit anything positive while having no problem jumping and supporting anything negative about Zen.

On topic: Most of the info says that the first chip to launch will be the 8C/16T. IF that is true, and from what we have so far it most likely is, I find it hard to believe that other chips will be clocked lower.

Unless of course we end up in a situation of AMD releasing "special" binned 8Cs first and then following with lower clocked 8Cs later. Which I guess is possible but also kind of a weird thing to do.

 

[KTE]

Surely that the guy who is behind CPUZ and Memtest86+ (that he designed using Memtest86 as basis) is someone who s credibility can be questionned by whoever post on any forum, that being said he knows insiders within both Intel and AMD and it is clearly stated on the articles of the last edition...

Franck is highly reliable, and a good friend. It's not his credibility being questioned here but peoples interpretations.

Sent from HTC 10
(Opinions are own)

 

[bjt2]

Frequency is not about process since at least 32nm.

Do Broadwell and Haswell have different FO4, by the way?

Frequency was not ever process alone. There is also FO4. Not only at 32nm. At 90nm there was Pentium 4 speed daemon. At 65nm other P4 version and if i remember well yonah or merom, that were high fo4 low power and low clock...

Broadwell and Haswell should have same architecture and so same relative FO4. Absolute FO4 is different, because the process is different. I don't know max OC but i think that from 22FF to 14FF there was little gain. Most of the gain was from 32 bulk to 22 ff...

He said they took the best of both zen and jag. You cant derive much from it regarding if this oc to 4 or 5GHz imo.
We have canard saying 5GHz on air. Not LN stability whatever crap. It means what it means. Its the same as kbl 5GHz on air. I find the rest nitpicking.
As for the Keller interview did you mention how he described i asume bd arch as trying to "make the ocean boil". Lol.

What can have taken from Bulldozer if not the low FO4? The low IPC? I don't think. He clearly stated that he took the speed from bulldozer. The one way is to have the same or better FO4.

That twitter though. What the hell is going on.

Also glofo's 14nm is IBM's finfet that will be used to make power9 but only uptil ~4GHz ranges .. I find these 5GHz@Air highly dubious.

Fo4 is what counts at same process...

 

[Thunder 57]

You do realize the binary code that's been asked about in that tweet is from an older publication from March 2016? Their response is basically, "we were right, weren't we?"

...

It's not the same page. The "Intel is using AMD GPUs" rumor has been somewhat confirmed lately, so it makes their new publication with the "Zen on air OC = 5GHz" code even more credible. This is the opposite of trolling. It seems your mind short-circuited for a moment, as I like to call these moments



It's a publication that has solid sources here and there, and has a track record for leaking accurate stuff. It's expected.

I would have to strongly disagree. They have a great track record, sure, but I think the stuff in binary is just for laughs. We will soon see.

I don't get it. 28nm BULK allow 4 base and 4.3 turbo and 4.9 overclock.
14nm is way better than 28nm bulk.
Now we must only know the FO4.
Hint: Keller speech. https://youtu.be/idRLZTy9Pio?t=5m stating they have put bulldozer DNA in Zen. This can only mean the FO4 and a long pipeline. It was even simplified! (6x1way scheduler vs 1x4 way scheduler)
With low FO4 and better process, Zen should reach higher frequencies than excavator...

14LPP is way better than 28 nm SHP. I don't expect a miracle though. It's a completely new uarch and we have no reference point. I'm going to stay conservative on frequency. If AMD proves me wrong, well, all the better!

 

[cytg111]

Fo4 is what counts at same process...

FO4? Moving in above my head here, but aint FO4 a submetric of IPC? Pipeline stages, latency per stage .. something like that?
Given that we know that IPC is ~Broadwell, what else is FO4 telling us ?

 

[krumme]

Its for the laughs but they hint its true
https://mobile.twitter.com/CPCHardware/status/814263696948162560

 

[witeken]

14nm is way better than 28nm bulk.

Not necessarily. The voltage/speed curve is a bit different for finfet. FinFET is not necessarily better than planar for high voltages, at least not the first gen.

 

[krumme]

Anyone noticed the frontpage on Canard magazine:
At the logo of Intel, and the arrow pointing downwards. In my translation:
" A drifting giant. The investigation of a disastrous strategy."
While at Ryzen its more like "A cracking comeback"

 

[KTE]

Not necessarily. The voltage/speed curve is a bit different for finfet. FinFET is not necessarily better than planar for high voltages, at least not the first gen.

There's so many things to consider with any particular process...

"Lower power" refers to Ioff.

Consider also:

Look at the transistor curves for Intels 22nm... And the differences for SP to HP, respectively. Then look above at the range of common problems according to the voltage used.



Sent from HTC 10
(Opinions are own)

 

[Dresdenboy]

for Zen the L3 holds the Tags for all data in the core L2's So you dont get the full 8mb per CCX as an eviction cache.
For Intel ring bus the L1 and L2 are inclusive in the L3 so its all cores L1+L2 but its not write through so the data in the L3 can be stale. https://en.wikipedia.org/wiki/MOESI_protocol

If they use a directory based cache coherency scheme, the tags in the L3 could even be split over the 4 subsections to realize some kind of banking.

Also they are all write back this time, where BD had a write through L1. I didn't understand why they did that. I didn't think there was much reason to use write through cache these days (simplicity?)

I think this was timing related.

Deeper pipeline would mean lower FO4, not similar. Lower IPC comes from various simplifications made to have low FO4 (like 6 simple schedulers instead of one fat scheduler)

Aside from that the lower IPC is also caused by having to split units over more stages. I think the FO4/IPC correlation is not that strict, as it is usually working for the same basic uarch (e.g. same branch predictor, same amount of IPRs, FUs, etc with just some adaption of buffer sizes). A different uarch might trade a lot of area and power to even stay at the same IPC or even increase it. BTW, a nice diagram showing the first mentioned relationship:

Source: http://microblog.routed.net/wp-cont...ircuits-for-the-ibm-power6-microprocessor.pdf

 

[Abwx]

"Lower power" refers to Ioff.

Not at all, Ioff is a byproduct because such devices have lower transconductance and higher gate threshold voltage, hence a lower Ioff but that s not the main point for their usage.

Low power means low transconductance but as a consequence also lower switching capacitance, the end result is a device that has limited max frequency but wich is less power hungry at moderate frequencies.

 

[bjt2]

FO4? Moving in above my head here, but aint FO4 a submetric of IPC? Pipeline stages, latency per stage .. something like that?
Given that we know that IPC is ~Broadwell, what else is FO4 telling us ?

FO4 can be independent of IPC. Usually high IPC architecture have high FO4, but it is not automatic.

I already explained that but in synthesis:
Make the best architecture you can, with high IPC and high FO4. Split the stages until you reach the desired FO4. Then you have increased the stages and the branch misprediction penality, but usually the branch predictor has high success ratio. For blender, for instance, the branches were 7% of the instructions and the branch misprediciton was under 2%. Even if you double the stages, you double the penality on 2% of 7% of instruction. So you lose IPC, but of a negligible quantity. You increase the power at same Vcore, because you need more transistors, but you need less vcore for same frequency. In the end you can increase the frequency, to have same power you should lower the vcore, and so if you double the stages, you can't double the frequency, for power constraints and only losing a few % IPC.

 

[bjt2]

Not necessarily. The voltage/speed curve is a bit different for finfet. FinFET is not necessarily better than planar for high voltages, at least not the first gen.

We are two nodes away. Anyway if I remember well, the problem of the 22nm FF of INTEL was that it had short fins and so thin depletion zone.

14nm solved this with taller fins, that allowed to have higher depletion zone and so lower the leakage and improve other features, like 2 fins instead of three etc...

I don't think that samsung/GF repeated the same error of INTEL with all this time...

 

[bjt2]

If they use a directory based cache coherency scheme, the tags in the L3 could even be split over the 4 subsections to realize some kind of banking.


I think this was timing related.


Aside from that the lower IPC is also caused by having to split units over more stages. I think the FO4/IPC correlation is not that strict, as it is usually working for the same basic uarch (e.g. same branch predictor, same amount of IPRs, FUs, etc with just some adaption of buffer sizes). A different uarch might trade a lot of area and power to even stay at the same IPC or even increase it. BTW, a nice diagram showing the first mentioned relationship:

Source: http://microblog.routed.net/wp-cont...ircuits-for-the-ibm-power6-microprocessor.pdf

Pentiun 4 had the right FO4 (13) to have max performance, but too low IPC: too few pipelines, no L1I cache relying on uop cache, too few decoders, and conceived for 32 bits and not 64 bits... A disaster... Then they switched to Yonah/Merom to be safe and not start over, that would have required much time...

 

[Abwx]

14nm solved this with taller fins, that allowed to have higher depletion zone and so lower the leakage and improve other features, like 2 fins instead of three etc...

They reduced the number of fins, at the end they have lowe Ioff bt more importantly transcondctance was heavily degraded, overall it s compensated by lower capacitance that allow to yield a total of 15% better perf/Watt, at least with the first iteration of this process.

I don't think that samsung/GF repeated the same error of INTEL with all this time...

If a short pipelined CPU using GF S 14nm can work at 2.41GHz/0.8V while Intel s CPUs work at 1.95GHz/0.8V then any first year university EE student will tell you that the former has 20% better transconductance...

 

[TheELF]

So they will release 8C chips, after the initial launch that will be running at base clocks lower than even the old ES that was used in this review?

No don't worry, they will just throw away any chip that runs slower(even 3.35 ones) because they have so much money that they just don't care...
Of course they will be binning their chips and release cheaper models at lower clocks,why on earth shouldn't they?

 

[bjt2]

They reduced the number of fins, at the end they have lowe Ioff bt more importantly transcondctance was heavily degraded, overall it s compensated by lower capacitance that allow to yield a total of 15% better perf/Watt, at least with the first iteration of this process.



If a short pipelined CPU using GF S 14nm can work at 2.41GHz/0.8V while Intel s CPUs work at 1.95GHz/0.8V then any first year university EE student will tell you that the former has 20% better transconductance...

Actually it was the NEON FPU of an ARM A53(?), 330mW of which 18 leakage and the other is dynamic.
It is a 2x64bit FPU. I estimated that the Zen FPU (4x128bit), implemented with the same FO4 (high, since is a synthetized ASIC) would draw about 1.2W and so a full CPU under 5W and so 32 zen core would be feasible at least at 2.41GHz in 180W... I posted also a graph of power/frequency scaling for that NEON FPU in which the power only tripled at 4.3GHz, respect to 2.41GHz. So under 15W/core at 4.3Ghz could be feasible. But this is an excess estimation, because a CPU does not draw 4x the power of the FPU and probabily Zen FO4 is not 30+ but way less....

EDIT: and the comparison you made is also more impressive, because the NEON FPU has 30+FO4, while we know that intel CPUs have about 26-28 FO4...

 

[bjt2]

No don't worry, they will just throw away any chip that runs slower(even 3.35 ones) because they have so much money that they just don't care...
Of course they will be binning their chips and release cheaper models at lower clocks,why on earth shouldn't they?

What make you think that the 3.4GHz was the top binning and not the low binning? They should only show a CPU that battled with a default 6900K, so a 3.4GHz sample would suffice. They hid also the max turbo, why don't hide also top bin frequency?...

 

[ecogen]

No don't worry, they will just throw away any chip that runs slower(even 3.35 ones) because they have so much money that they just don't care...
Of course they will be binning their chips and release cheaper models at lower clocks,why on earth shouldn't they?

My issue was with the clocks, if anything with the info we have so far 3.4 should be the "slower" chips.