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ZEN ES Benchmark from french hardware Magazine

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inf64

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Mar 11, 2011
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"No hard data but friends have told me it clocks well. If 3.4 is launch speeds, 5 should be no problem for the pros. Haven't heard of any speed path issues yet but you never know until the LN2 guys get ahold of it.

-Charlie
"

My guess is 4.5 Ghz now looks very realistic on air for 24x7. I think AMD will aim for max single core turbo of 4.2 Ghz with final release chips to remain competitive against Skylake and Kabylake in gaming.
Charlie also said:
Charlie @ RWT said:
> I assume that the missing features have to do with clock and power management, not microarchitecture, right?
>

Yeah. Turbo was one, some power management was another, and some minor stuff. It is in the CPU just that the stepping we used was either disabled or buggy. This is normal development stuff, not anything major and most of it seems to be firmware and optimizations, not basic functionality.

I am aware of the open bug counts on A1 and A2 and am very optimistic based on the changes. The next step (A3/4th rev of Zen) should have the last few stamped out long before release. It was stable enough to play Doom on last June so....
So last June we had A2 stepping and CanardPC was playing with (I believe) A0 at the end of November. So AMD seeded just the initial stepping to mobo partners for platform verification purposes. AMD should have taped out A3 or even A4 by now and that is probably the reason why Fottemberg @ BitsNChips (and other people) are talking about higher frequencies as of late.

If AMD can launch a 8C/16T chip with ST Turbo >4Ghz, then it will be a bullseye hit.
 

raghu78

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Aug 23, 2012
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Charlie also said:

So last June we had A2 stepping and CanardPC was playing with (I believe) A0 at the end of November. So AMD seeded just the initial stepping to mobo partners for platform verification purposes. AMD should have taped out A3 or even A4 by now and that is probably the reason why Fottemberg @ BitsNChips (and other people) are talking about higher frequencies as of late.

If AMD can launch a 8C/16T chip with ST Turbo >4Ghz, then it will be a bullseye hit.
http://seekingalpha.com/article/3967192-advanced-micro-devices-amd-lisa-t-su-q1-2016-results-earnings-call-transcript?part=single

" I'm also pleased to share that we are making excellent progress on our strategy to reestablish our presence in the datacenter market, as we successfully passed several key milestones related to our next-generation Zen-based server processor. The Zen silicon running in our bring-up labs is meeting our expectations, and priority customer sampling is on track to begin this quarter in advance of datacenter system availability in 2017."


Zen taped out sometime in early Q1 2016 and was sampled to server customers in Q2 2016. It was demoed first at Computex 2016 , then in Aug 2016 (around IDF 2016) running at 3 Ghz and now in Dec 2016 at New Horizon event at 3.4 Ghz. AMD said that they are still doing optimizations at this event so I am guessing there are still firmware optimizations to be done. I am pretty sure final A3 stepping with optimized firmware is likely to be ready by CES 2017.

Normally it takes 3-4 months to go from one stepping to another . So if we put A0 at Jan/Feb 2016 it agrees with a Dec 2016 /Jan 2017 timeline for A3 stepping. The mass production should start early next quarter and we might see a late March launch.
 
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Jun 19, 2012
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People should keep expectations reasonable. All AMD has promised is a processor that is competitive with the 6900k and nothing else. 5ghz on air is unrealistic, maybe 4ghz on air and 5ghz with water cooling.
 

el etro

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Jul 21, 2013
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So last June we had A2 stepping and CanardPC was playing with (I believe) A0 at the end of November. So AMD seeded just the initial stepping to mobo partners for platform verification purposes.
So, Zen was really meant to be a 2016 product. too many revisions to the design is a bit of out of luck IMO.
 

witeken

Diamond Member
Dec 25, 2013
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If it did readily 5GHz, wouldn't AMD have demoed that? Because BDW can't do that at all, it only goes to 4.3GHz or so I've heard. That would have been pure Intel demolition right there. No way AMD would leave that opportunity behind.
 

Dresdenboy

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Jul 28, 2003
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citavia.blog.de
But is that possible? Naples dies destined for an MCM package would possibly have different metal layers? o_O
That's the trick. The Stilt already said, that there will only be one die (to rule them all). There will be some necessary fusing/AGESA stuff to setup those dies accordingly. There just need to be enough GMI/Data Fabric links plus some smart layout to do the Lego building stuff.

Just think of Athlon 64, single die Opterons, or Magny Cours, a two die MCM. An Athlon 64 had one HT link, but the die contained three. It was the same die as used for Opterons (even the same steppings). That happened for multiple generations incl. Magny Cours using 2 Istanbul/Thuban dies.

Examples:
Thuban die (with labels, count the HT links): http://pclab.pl/zdjecia/artykuly/mbrzostek/thuban/pix/thuban_die_big.jpg
One Magny Cours die: http://www.qdpma.com/CPU_files/MagnyCours_layout.png
Shanghai: https://www.techpowerup.com/img/08-06-25/shanghaimap.jpg
Deneb & Propus: http://www.hartware.de/media/news/47000/47137_2b.jpg
Interesting: Deneb has 4 HT links while Propus has just one (and no L3 - further cost optimization).
 

CatMerc

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Jul 16, 2016
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If it did readily 5GHz, wouldn't AMD have demoed that? Because BDW can't do that at all, it only goes to 4.3GHz or so I've heard. That would have been pure Intel demolition right there. No way AMD would leave that opportunity behind.
Perhaps they simply didn't have silicon capable of that? Fottemberg claims that the "higher than expected" frequency chips are the latest revision, and who knows when that happened. And honestly, we can't know how AMD will operate with a trump card - Its been a damn long time since they had something of the sort, and leadership changed a ton since then.
 
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Sven_eng

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Nov 1, 2016
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I'll just say this.

Zen being a hit is good for everyone, why the intel fanboi's are getting there panties in a bunch really defies all logic, perhaps viral marketing truly is making a combeack and its going to be like the rollo days all over again. Or the poster saying they are really intel investors is bang on, cause then it does make sense.
Many Intel fans are emotionally invested in the downfall of AMD because they have been downplaying AMD's capability for years on forums like this. :) But it is good to see many who are seemingly "pro intel" and "anti amd" are still impressed with what AMD has seemingly done with Zen. :)

It's very true too that Intel stockholders have material investments in the failing of AMD. This one is very strange however as they could make much more money on shorting Intel's downfall.

That said we have seen absolutely nothing proving anything about IPC, sure this is a credible source and it very well may be legit, but until the NDA is up we cant trust anyone, thats the simple truth. I want to believe this as much as anyone but we still have a few weeks to go. All we have officially is the demo from last week that didnt show much really.

Also some mobo manufacturer better be planning on making a mobo with beefy VRM's i want to see what these bad boys can do at launch! I think hitting 5Ghz on air prime stable is a pipe dream but a guy can hope.
CPC can be trusted more than AMD's own benchmarks
 

krumme

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Oct 9, 2009
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So, Zen was really meant to be a 2016 product. too many revisions to the design is a bit of out of luck IMO.
Naa think again. If Fottemberg is right and they exceeded anticipated freq with the latest revs the bugs might even have have helped them launch a very compettitive product because it have forced those rev !

I always feared and expected that amd due to cash constraints and pressure would launch a half baked product going for shortsighted TTM goals. Imo polaris looks like it also on driver side. Now it looks like they did go all the way for zen and then some.

Now this autum they solved their cash and payment problems completely. From where i am placed if there there is a single parameter that defines the freedom you have to run your business thats excactly it. Without cash you obviously cant do anything new from sales to product development but it also creeps into the risk profile you can manage even products that is nearly ready. At the top level its mentally choking.

Gitting rid of the dept thats was due in the next comming years they had the cash to continue making rev and take their time. The bugs perhaps helped them go there ;)

Innovation and development is sometimes a bit weird.
 
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bjt2

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Sep 11, 2016
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Arghhh this is just in 2 pages! Same incessant words, over and over and over and over again. These parroted posts of yours form like 50% of this thread. If you keep going, Anand will need to sell all his remaining hair to fund bigger storage... What is the point of your endless repeat mode?

We get it, you love AMD and you love them to have 4.5GHz 8C 95W BDe IPC launch and improve to 5GHz soon trampling Intels best by 30%...

Everything about your posts and the posting style is reminding me of extreme fanatics, pardon my expression. You sound just like this guy: http://semiaccurate.com/forums/showpost.php?p=278509&postcount=4807


Insulting other members is not allowed
Markfw
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(Opinions are own)
If other members here keep saying things that don't fit the data and reasoning i was giving here, i keep repeating, with other words, because maybe i was not clear the other times i said that.

If you say X, without proof, and i have proof that X is false, why i must stay quiet?
Keep making unsupported claims and I will continue to respond with facts.
Continuing to make unsupported claims will not make them true. And after CES, this game will CEaSe... Because the truth will be out...

Spreading false or unsupported informations is what leads to big surprised guys: no one ever expected 3.4GHz+ base clocks for Zen. Why? Because there are dozens of persons shouting sentences like "AMD can't do a chip with higher clock of INTEL's because GF process is worse than INTEL's", completely forgetting FO4. And Excavator's clock and overclocks on a 28nm BULK process with HDL libraries are a perfect example. 4 base, 4.3 turbo and 4.9 air OC is not bad. And this was due only to FO4. Because even Haswell on 22nm did not reach the clocks of A12 9800. And Excavator reached this also in 65W TDP! What else can be? 28nm BULK better than 22nm FinFet? Obviously no!
We have already reached better clock than BWE: 6900K has 3.2Ghz base and RyZen will have more than 3.4GHz base clock. With less TDP. On a worse process. How is this possible? Is low power GF process better than high power INTEL process? Or mabybe it's the FO4? We have indication that the FO4 will be low: 19 stage integer pipeline, 6xone way iteger scheduler, 2 stages floating point scheduler and Keller statements...
 
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bjt2

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See my answer above. I think, there will be one or more Ryzen models with a base clock of at least 3.4GHz, but not necessarily no cheaper models with base clocks below this mark. I think TheELF meant future products' clock distribution, while you are analyzing the demo'ed frequency.
There will certainly be bins clocked below 3.4GHz, but in the future, probabily. Because usually they launch top bin first (with low yield), storing low binned parts for later hard launch, or, as you say for Naples. Now the only thing to know is how many bins they will launch first... Low clocking parts may also be low leakage parts and these can be conveniently saved for Naples or Snowly owl...
 

krumme

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Oct 9, 2009
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If other members here keep saying things that don't fit the data and reasoning i was giving here, i keep repeating, with other words, because maybe i was not clear the other times i said that.

If you say X, without proof, and i have proof that X is false, why i must stay quiet?
Keep making unsupported claims and I will continue to respond with facts.
Continuing to make unsupported claims will not make them true. And after CES, this game will CEaSe... Because the truth will be out...

Spreading false or unsupported informations is what leads to big surprised guys: no one ever expected 3.4GHz+ base clocks for Zen. Why? Because there are dozens of persons shouting sentences like "AMD can't do a chip with higher clock of INTEL's because GF process is worse than INTEL's", completely forgetting FO4. And Excavator's clock and overclocks on a 28nm BULK process with HDL libraries are a perfect example. 4 base, 4.3 turbo and 4.9 air OC is not bad. And this was due only to FO4. Because even Haswell on 22nm did not reach the clocks of A12 9800. And Excavator reached this also in 65W TDP! What else can be? 28nm BULK better than 22nm FinFet? Obviously no!
We have already reached better clock than BWE: 6900K has 3.2Ghz base and RyZen will have more than 3.4GHz base clock. With less TDP. On a worse process. How is this possible? Is low power GF process better than high power INTEL process? Or mabybe it's the FO4? We have indication that the FO4 will be low: 19 stage integer pipeline, 6xone way iteger scheduler, 2 stages floating point scheduler and Keller statements...
If we had used Ocxam Razor its pretty straightforward with the arguments you presented that we should have expected higher frequency when we knew the facts.
The counter argument was eg expected high ipc, gf 14lpp freq as shown on the gfx and in general prior gf execution and lack of amd funds.
Now eg the 19 stages pipeline obviously is there for a reason and for an expected process performance. The designers is not stupid (even if some tried to make the ocean boil...) so the most straight forward explanation having the least asumptions was higher freq.

Now i am happy to say you were right and i was wrong. Not only because i get more performance for my hobby but because it makes me strong saying so. Not the weak sauce we see all over. I know its not easy but some people need to get a serious push so they can move on.
 

bjt2

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Sep 11, 2016
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https://translate.google.it/translate?hl=it&sl=auto&tl=en&u=http://www.cpchardware.com/cpc-hardware-n31-precisions-elucubrations/

Clarifications of canardPC:

- +35% performance on Piledriver. 1c/2t vs 1m/2t, so +35% includes smt vs cmt penality. +40% ST IPC can still be correct.

- hidden raw data: to avoid reveal to AMD their source

- 2 bioses/agesa. They published the best results. The worse result was ~sandy bridge IPC. Still some bugs in uop cache and SMT. Retail should be better.

- 5GHz air OC. Confirmed. Source performed it, not them. 1 core only, because MB VRMs did not manage to support 8 cores. It seemed that was not CPU fault. Big heatsink and air OC. BIOS have unlocked multiplier. 0.25x step. I suppose 100mhz "FSB", to have 25mhz increments with 0.25x multiplier increment...
 

iBoMbY

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Nov 23, 2016
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At least close to 5 GHz. I would be more than happy if it would run stable at 4.5 GHz on all cores in the end. I guess it wouldn't hurt to invest in a mainboard with a good VRM solution - I hope they will be available from the start.
 

bjt2

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Sep 11, 2016
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At least close to 5 GHz. I would be more than happy if it would run stable at 4.5 GHz on all cores in the end. I guess it wouldn't hurt to invest in a mainboard with a good VRM solution - I hope they will be available from the start.
This was an A0 ES, probabily of at least 6 moths ago. I would hope that retail steps will draw slightly less power and allows slightly higher overclocks... Or at least 8c overclocks...
 

krumme

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If more or beefier vrm is needed to oc to 5GHz all core everyone and his brother will make it. 5 sounds much better than 4.8 even if the difference is nill.
 

IntelUser2000

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Oct 14, 2003
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Spreading false or unsupported informations is what leads to big surprised guys: no one ever expected 3.4GHz+ base clocks for Zen. Why? Because there are dozens of persons shouting sentences like "AMD can't do a chip with higher clock of INTEL's because GF process is worse than INTEL's", completely forgetting FO4. And Excavator's clock and overclocks on a 28nm BULK process with HDL libraries are a perfect example.
Clock advantage at the absolute high end due to process died a few years ago. Intel has practically zero advantage there. Design matters much more now. It used to be by just looking at benchmarks to distinguish what process generation was used for a product. Because there was a clear gap. Without a vast design advantage, process gap couldn't be closed. Few years ago, that stopped. It's like in every other industry now. The Moore's Law "magic" is gone. No breakthroughs on the horizon. No single answer solution coming. Meanwhile everything is becoming harder and costlier.

It seems if you read other parts of that CanardPC article, AMD's comeback product is going to arrive at a moment when Intel will be at its worst ever.

Interestingly, the last time AMD had a new architecture which changed the tides for AMD was the original Athlon.
 
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TheELF

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Dec 22, 2012
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https://translate.google.it/translate?hl=it&sl=auto&tl=en&u=http://www.cpchardware.com/cpc-hardware-n31-precisions-elucubrations/

Clarifications of canardPC:

- +35% performance on Piledriver. 1c/2t vs 1m/2t, so +35% includes smt vs cmt penality. +40% ST IPC can still be correct.
http://www.cpchardware.com/cpc-hardware-n31-precisions-elucubrations/
The comparison concerns a single core with CMT or SMT in both cases (it is to say one core / 2 threads for Zen and 1 core / 2 clusters for the FX-8370). In the latter case, the definition of "core" and "cluster" is the technical definition (as explained in this patent AMD, page 6) and not in the marketing definition invented later.
Yeah, for anybody who thinks that it's impossible for AMD to pull the same crap with SMT,it's just a matter of how they state it in the patents.
 

bjt2

Senior member
Sep 11, 2016
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Clock advantage at the absolute high end due to process died a few years ago. Intel has practically zero advantage there. Design matters much more now. It used to be by just looking at benchmarks to distinguish what process generation was used for a product. Because there was a clear gap. Without a vast design advantage, process gap couldn't be closed. Few years ago, that stopped. It's like in every other industry now. The Moore's Law "magic" is gone. No breakthroughs on the horizon. No single answer solution coming. Meanwhile everything is becoming harder and costlier.

It seems if you read other parts of that CanardPC article, AMD's comeback product is going to arrive at a moment when Intel will be at its worst ever.

Interestingly, the last time AMD had a new architecture which changed the tides for AMD was the original Athlon.
Intel was burnt (in all ways... :D ) by the P4 fiasco and keep the safe route of a consolidated architecture: the Pentium Pro/P6. And made only incremental evolutions. Yes: even integrated NB is an incremental evolution. Zen has the same coprocessor like organization of the first K7, but with evoluted pipelines and scheduler, not mentioning uop cache and stack engine/memfile. It's a brand new architecture, but with legacy of the k7 route. They apparently changed the FO4, though, because the K7/8 can't push clocks so high. It's not a blind change. Even keller in the youtube video sayd that: we know how to make high speed design. We don't start from scratch. But they have departed further from old design (bulldozer), partially returning on their steps...
 

krumme

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Oct 9, 2009
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I say: "I want the speed of a Ferrari and the price of a Fiat. I want the best dna of both. Now !"
.
.
.

Wtf nothing happened. Can you help me guys?
 

bjt2

Senior member
Sep 11, 2016
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I say: "I want the speed of a Ferrari and the price of a Fiat. I want the best dna of both. Now !"
.
.
.

Wtf nothing happened. Can you help me guys?
My bad i think that if zen goes like a Ferrari, it will cost like a Ferrari... But will draw same power as a Fiat, it seems...
 

krumme

Diamond Member
Oct 9, 2009
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My bad i think that if zen goes like a Ferrari, it will cost like a Ferrari... But will draw same power as a Fiat, it seems...
Yeaa. Thet are good underway of doing it i must say. Some Keller pixie dust thats for sure. Its just damn hard in reality to find that balance and p4 and bd proves it. For a starter you eg need a stellar branch predictor and fetcher. Nothing less.
I am just trying to say it was not that easy to forecast beforehand.
 

The Stilt

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Dec 5, 2015
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Charlie also said:


So last June we had A2 stepping and CanardPC was playing with (I believe) A0 at the end of November. So AMD seeded just the initial stepping to mobo partners for platform verification purposes. AMD should have taped out A3 or even A4 by now and that is probably the reason why Fottemberg @ BitsNChips (and other people) are talking about higher frequencies as of late.

If AMD can launch a 8C/16T chip with ST Turbo >4Ghz, then it will be a bullseye hit.
There are no Ax steppings, just A0 at different node versions.
Of course it doesn't imply that A0 would or won't be the stepping Ryzen is going to launch with ;)
 

bjt2

Senior member
Sep 11, 2016
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Yeaa. Thet are good underway of doing it i must say. Some Keller pixie dust thats for sure. Its just damn hard in reality to find that balance and p4 and bd proves it. For a starter you eg need a stellar branch predictor and fetcher. Nothing less.
I am just trying to say it was not that easy to forecast beforehand.
Before knowing the architecture and the pipeline stage count, my forecasts were prefixed with a big IF... IF FO4 is same than BD, then yadayada...
Because 14nmFF is way better than 28nm BULK and i never believed of a regression in frequency. And if Zen was not better than BD, why don't produce a simple BD shrink? The only reason is that Zen is better than BD...
 
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