Intel ES usually has bugs as well. I remember Sandybridge ES has 0 performance uplift against Nehalem, but one year later the retail are a lot different. It all depends on how much time left before retail launch, both bug itself and clock could still be determined by respin, even sometimes both bug and clock could derive from same factor, such as silicon itself.
As for TLB bug on Phenom. IIRC this bug was still on B2 stepping which need fix, after that 3 months later B3 stepping no longer need any fix and perform as good as non-fix B2. I think if SMT and uop bug cause Zen doesn't come sooner, then we don't need to worried, just wait for the real launch though.
BTW, unlike TLB, both SMT and uop has nothing could be 'disabled', isn't it?
As for TLB bug on Phenom. IIRC this bug was still on B2 stepping which need fix, after that 3 months later B3 stepping no longer need any fix and perform as good as non-fix B2. I think if SMT and uop bug cause Zen doesn't come sooner, then we don't need to worried, just wait for the real launch though.
BTW, unlike TLB, both SMT and uop has nothing could be 'disabled', isn't it?
