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ZEN ES Benchmark from french hardware Magazine

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itsmydamnation

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Feb 6, 2011
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Great information. I remember reading about MESI years back but I haven't really kept up with cache coherency and multicore. So the L3 only holds the tags, and can act almost like a pointer to the valid data? Makes sense. Also they are all write back this time, where BD had a write through L1. I didn't understand why they did that. I didn't think there was much reason to use write through cache these days (simplicity?).

This leads me to a further question; Are both MOESI and MESIF two different ways of accomplishing the same thing?
the difference covered here https://en.wikipedia.org/wiki/MESIF_protocol

as to BD cache design, god knows what went on there.
 

krumme

Diamond Member
Oct 9, 2009
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Keller said this 2 years ago: https://www.youtube.com/watch?v=idRLZTy9Pio&feature=youtu.be&t=5m1s

Zen was thought from the beginning as speed daemon as bulldozer (low FO4) and low power as Jaguar...
What strikes me looking at it today vs 2 years ago is how he multiple times expressed how they had learned from working on arm. Its also his last words. Knowledge development is crucial for him and that in particular is at top of his mind bar none. The example of how they thought they found an error in arm with their tools and it turns out it was an error in their own tools is both fun and telling.
 

Opcode

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Mar 27, 2015
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Also they are all write back this time, where BD had a write through L1. I didn't understand why they did that.
According to computer weekly.
  • Write-through cache directs write I/O onto cache and through to underlying permanent storage before confirming I/O completion to the host. This ensures data updates are safely stored on, for example, a shared storage array, but has the disadvantage that I/O still experiences latency based on writing to that storage. Write-through cache is good for applications that write and then re-read data frequently as data is stored in cache and results in low read latency.
AMD went with write-back in Zen to save power.
 
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witeken

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Thunder 57

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According to computer weekly.
  • Write-through cache directs write I/O onto cache and through to underlying permanent storage before confirming I/O completion to the host. This ensures data updates are safely stored on, for example, a shared storage array, but has the disadvantage that I/O still experiences latency based on writing to that storage. Write-through cache is good for applications that write and then re-read data frequently as data is stored in cache and results in low read latency.
AMD went with write-back in Zen to save power.
Right. Maybe I missed it, but I was wondering why they went to a write-through L1 in BD to begin with?

You've been trolled :D

Zen does not run @5GHZ, peeps.

https://twitter.com/CPCHardware/status/814263696948162560

It says

Intel GPU = AMD

They're just joking around. Text being put in a binary translator does not make it reliable, or true.
Haha, well at least they're having some fun with it. Something there didn't look right. Glad we have our answer.
 

itsmydamnation

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majord

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witeken

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Dec 25, 2013
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Hasnt Intel been rumored to be in a deal with AMD for GPU tech IP licensing? If so, Im not sure it is a troll or prophecy.
Still, the smiley is "Smiling face with open mouth and cold sweat".

Edit: And it's from March '16.
 

Tuna-Fish

Golden Member
Mar 4, 2011
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Thank you, that's exactly what I was looking for. Since it's in there as well, I thought the decision for an inclusive cache for Zen was interesting. What surprised me was the L3 not being inclusive (though not exclusive either, IIRC. I believe on previous AMD designs they referred to this as "non-inclusive" L3). The reason I figured they would go all inclusive was because of this:

The other consideration is that Intel only loses 256KB per core in the L3, whereas if AMD used an inclusive L3 it would lose 512KB per core. Any thoughts on this anyone?
AMD has stated that the L3 knows what lines are known in the caches below it. To me, this implies that the L3 has extra tags for them.
 

Abwx

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Apr 2, 2011
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It says

Intel GPU = AMD

They're just joking around. Text being put in a binary translator does not make it reliable, or true.

Edit: The font sized looked kinda overkill, even for a title.
Because on the current CPC edition and the article about intel it is written that :

Intel is currently working on a "multichip package" (MCM) integrating an Intel CPU and an AMD GPU. So this is confirmed guys.

????
 
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.vodka

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Dec 5, 2014
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You've been trolled :D

Zen does not run @5GHZ, peeps.



https://twitter.com/CPCHardware/status/814263696948162560

It says

Intel GPU = AMD

They're just joking around. Text being put in a binary translator does not make it reliable, or true.

Edit: The font sized looked kinda overkill, even for a title.

You do realize the binary code that's been asked about in that tweet is from an older publication from March 2016? Their response is basically, "we were right, weren't we?"





It's not the same page. The "Intel is using AMD GPUs" rumor has been somewhat confirmed lately, so it makes their new publication with the "Zen on air OC = 5GHz" code even more credible. This is the opposite of trolling. It seems your mind short-circuited for a moment, as I like to call these moments ;)

Hasnt Intel been rumored to be in a deal with AMD for GPU tech IP licensing? If so, Im not sure it is a troll or prophecy.
It's a publication that has solid sources here and there, and has a track record for leaking accurate stuff. It's expected.
 

.vodka

Golden Member
Dec 5, 2014
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I stand corrected.

Do keep in mind though an earlier leak pointed to 4.3GHz.
Sure.

The statement, as I understand, is to be taken that Zen's clock ceiling is above 4GHz. Of course it won't do 5Ghz for 24/7 usage like delidded Kabylake does. If it does reach 5GHz, it won't be at safe voltages. Hell, I don't think KBL's 5GHz is safe at 1.3-1.4v for long term usage, those are voltages we were using back then on 32-45nm CPUs, not much more fragile 14nm based CPUs.

They need clock speed to close the 5-20% gap to the 6900k (especially on those apps that make use of the superior AVX/2 hardware on Intel cores as few as they are, as they skew the % a lot) for the 8C16T part, and they also need even more clock speed to put up some kind of a fight to 4C8T 6700K/7700K (based on the half working ES results from their own numbers on the publication).


I'd be completely alright with 4.3GHz (that is for an A0 ES of a first gen design on a not that stellar process that has lots of tweaking to be done on its next steppings, on top of a not finished platform at the moment), if that is for the 8C16T part when OC'd. 4C8T/6C12T should be able to do 200 or 100MHz higher.
 
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bjt2

Senior member
Sep 11, 2016
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Yes you should totally trust FPiednoel when it comes to AMD because he would know right.

I have to go back to my default position of why not? There is nothing i can see that says Zen cant hit 5.0ghz on air. We know lots of performance comes from predictors/prefetch/uop cache and far better L2. None of those look clocking liming, they broke down the really latency sensitive area into 6 individual schedulers and we know what bulldozer could hit with a 4 wide scheduler. One big unknown is what the iPRF looks like but the fPRF in BD has a very larger amount of read and write ports and it doesn't limit clock.

So im not going to say Zen cant hit 5.0ghz on air but the people who are can you be specific as to why?
They will say that is because 14nm is low power, because INTEL can't, so neither AMD with a worse process can't, because if an architecture has high IPC, like INTEL, can't have lower FO4 and so can't clock higher than INTEL, etc...
Obviously all false statements. And I have already explained why for each of them... The short answeris : yes, you can (make an high IPC architecture with a low FO4 and hence high clock).
 

bjt2

Senior member
Sep 11, 2016
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While I disagree with him on many fronts, he is a verified competing professional knowing a lot more about real world chip tech than most here.

His statements are no different to Lisa et al. Both biased, both ulterior motives, both PR.

BTW I didn't say it can't OC to xMHz. Ever.

I said it won't launch at those MHz at 95W (since the very start).

Sent from HTC 10
(Opinions are own)
If a 300+mmq chip can go at xGHz at 95/125W and max air OC is 5.xGHz, why a <200mmq (so more area per mmq) with a better process that OC at air at 5GHz can't go higher?

If a so small chip can OC at 5GHz, probabily it will do this with lower power than the 300+mmq chip, because it will melt, otherwise... So same clock with less power, and so at same power should clock more...
 

bjt2

Senior member
Sep 11, 2016
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Sure.

The statement, as I understand, is to be taken that Zen's clock ceiling is above 4GHz. Of course it won't do 5Ghz for 24/7 usage like delidded Kabylake does. If it does reach 5GHz, it won't be at safe voltages. Hell, I don't think KBL's 5GHz is safe at 1.3-1.4v for long term usage, those are voltages we were using back then on 32-45nm CPUs, not much more fragile 14nm based CPUs.
You are assuming that Zen has same FO4 than KabyLake... Why do you think that?
 

TimCh

Member
Apr 7, 2012
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You are assuming that Zen has same FO4 than KabyLake... Why do you think that?
Zen has lower IPC and a deeper pipeline than KabyLake - similar FO4 seems absolutely possible.

Sendt fra min SM-G928F med Tapatalk
 

bjt2

Senior member
Sep 11, 2016
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Zen has lower IPC and a deeper pipeline than KabyLake - similar FO4 seems absolutely possible.

Sendt fra min SM-G928F med Tapatalk
Deeper pipeline would mean lower FO4, not similar. Lower IPC comes from various simplifications made to have low FO4 (like 6 simple schedulers instead of one fat scheduler)
 

KTE

Senior member
May 26, 2016
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If a 300+mmq chip can go at xGHz at 95/125W and max air OC is 5.xGHz, why a <200mmq (so more area per mmq) with a better process that OC at air at 5GHz can't go higher?

If a so small chip can OC at 5GHz, probabily it will do this with lower power than the 300+mmq chip, because it will melt, otherwise... So same clock with less power, and so at same power should clock more...
You're right, tag team. Faith makes that 8C 5GHz 95W sound so easily doable

None of your underlying assumptions have any hard data behind them... As explained a tireless amount of times. Unlinked, unconnected or ambiguous data exists but your link/jump from one to another requires a HUGE leap of... Faith.

Sent from HTC 10
(Opinions are own)
 
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