Question Zen 6 Speculation Thread

[Covfefe]

According to JEDEC, LPDDR6-14400 has 2x the bandwidth of LPDDR5X-9600. https://www.jedec.org/sites/default/files/Brett Murdock_FINAL_Mobile_2024.pdf

Extrapolating from that. A 192-bit LPDDR6 memory bus has 1.33x the bandwidth of a 128-bit LPDDR5/X memory bus of the same per-pin speed.

A LPDDR6-10667 192-bit config (which should be the base LPDDR6 config for laptops) has 89% as much bandwidth as Strix Halo.

 

[MerryCherry]

A 192 bit LPDDR6 bus nets 227.56 GB/s.

Yes, that's 89% of STXH's 256 GB/s.

So Medusa Halo with 384 bit will have 455 GB/s. A 77% increase.

 

[adroc_thurston]

A LPDDR6-10667 192-bit config (which should be the base LPDDR6 config for laptops) has 89% as much bandwidth as Strix Halo.

see issue is it gotta be FP10, which means 128b L5x only.

 

[MerryCherry]

see issue is it gotta be FP10, which means 128b L5x only.

When will this Medusa premium part release?

I heard Medusa Halo will be CES 2028, so there the time will be ripe for LPDDR6 adoption.

Android flagships with LPDDR6 are slated to debut in 2026Q4, and those will probably be the only consumer devices with LPDDR6 throughout 2027.

 

[adroc_thurston]

When will this Medusa premium part release?

I heard Medusa Halo will be CES 2028, so there the time will be ripe for LPDDR6 adoption.

This has absolutely nothing to do with mem timelines and everything to do with socket pinouts.
FP10 is DDR5/LPDDR5 socket.

 

[Tuna-Fish]

If the part has a combo PHY, I would assume AMD would come out with some new socket for it to use the better RAM. Possibly not at initial release, if LPDDR6 is still very expensive.

I would not take leaks that the Medusa Premium supports FP10 as proof that it only supports it.

 

[adroc_thurston]

If the part has a combo PHY, I would assume AMD would come out with some new socket for it to use the better RAM. Possibly not at initial release, if LPDDR6 is still very expensive.

I would not take leaks that the Medusa Premium supports FP10 as proof that it only supports it.

oh they're definitely gonna stuff it into the halo socket (the gutted 128b stxH SKU exists), but that's memey.
The point is very much stuffing discrete compete into commodity sockets.

 

[marees]

That's not how it works. Both of the combo PHYs announced so far keep the amount of channels constant between the memory types, not the width of the interface. Because all the lines other than data lines would need to be increased for more channels, and you'd have to do weird remapping between data lines of adjacent channels for different widths. (Also, because of changes in how LPDDR6 works, a wider bus is cheaper with LPDDR6 than with LPDDR5X.) A device using such a combo PHY that supports 192-bit LPDDR6 can only support 128-bit LPDDR5X.

so if I understood this correctly the medusa premium in a FP10 socket is restricted to 128bit lpddr5x but in a different (strix halo like) socket, it can go to 192 bit lpddr6 ?

for the AT4 based 10050xt, AMD would have the option of both 128 bit lpddr5x & 192 bit lpddr6 ??

 

[adroc_thurston]

so if I understood this correctly the medusa premium in a FP10 socket is restricted to 128bit lpddr5x but in a different (strix halo like) socket, it can go to 192 bit lpddr6 ?

yes.

for the AT4 based 10050xt, AMD would have the option of both 128 bit lpddr5x & 192 bit lpddr6 ??

also yes. but no, DT one needs all the membw they can muster.

 

[branch_suggestion]

oh they're definitely gonna stuff it into the halo socket (the gutted 128b stxH SKU exists), but that's memey.
The point is very much stuffing discrete compete into commodity sockets.

The really funny thing would be if AT4 was compatible with the MDSH SoC tile.

 

[adroc_thurston]

The really funny thing would be if AT4 was compatible with the MDSH SoC tile.

you mean the MID?

 

[branch_suggestion]

you mean the MID?

Whatever it is called yeah.

 

[adroc_thurston]

Whatever it is called yeah.

Yeah?
AMD hates spending tapeouts on stuff.

 

[ToTTenTranz]

So if Halo supports 384bit LPDDR6 in its socket, Premium can have a version that goes into Halo's socket and support 192bit LPDDR6 as well?


I get that it's releasing at a time when LPDDR6 still isn't available, but FP10 just seems awfully short sighted at this point.
It just means anything that succeeds Medusa past 2028 for drop-in replacements will need to use LPDDR5X (which will be 6 years old at that point), so realistically FP10 is probably for Medusa Point/Premium alone.

 

[branch_suggestion]

So if Halo supports 384bit LPDDR6 in its socket, Premium can have a version that goes into Halo's socket and support 192bit LPDDR6 as well?

Yeah, pretty nifty reuse and allows for a wider ASP variety in a given design, something OEMs appreciate.
This is important when taking on NV laptop slots.

I get that it's releasing at a time when LPDDR6 still isn't available, but FP10 just seems awfully short sighted at this point.
It just means anything that succeeds Medusa past 2028 for drop-in replacements will need to use LPDDR5X (which will be 6 years old at that point), so realistically FP10 is probably for Medusa Point/Premium alone.

L5X is gonna be around for a very long time, will steadily trickle down the pricing ladder but high volume stuff won't switch to LP6 until 2030+

 

[Tuna-Fish]

The point is very much stuffing discrete compete into commodity sockets.

I just honestly find the Medusa Premium on LPDDR5X to be an uninteresting product. AMD has been on a roll on it recently, but they are not going to improve memory efficiency that much in a single generation. I expect it will be the fastest 128b LPDDR5X APU on the market... ... and that this will actually not be all that great. LPDDR6 would add enough membw to let it properly differentiate.

 

[marees]

I just honestly find the Medusa Premium on LPDDR5X to be an uninteresting product. AMD has been on a roll on it recently, but they are not going to improve memory efficiency that much in a single generation. I expect it will be the fastest 128b LPDDR5X APU on the market... ... and that this will actually not be all that great. LPDDR6 would add enough membw to let it properly differentiate.

I see lpddr5x as a huge positive for medusa premium given the sky high memory prices — & open ai bankruptcy unlikely to happen before 2030

 

[basix]

It really depends on the speed of the LPDDR5X modules. 8.5...9.6 Gbps are getting standard. 12.7 Gps is the ceiling. Strix Point mostly uses 7.5 Gbps modules and many notebooks also slow 5.6 Gbps modules.

• 8.5...9.6 Gbps = 1.14...1.28x bandwidth vs. 7.5 Gbps
• 10.7...12.7 Gbps = 1.43...1.69x bandwidth

The bigger L1 and L2 caches should be very effective. Compared to Strix Point without MALL it will be a very decent upgrade in bandwidth efficiency.
If then the universal compression comes into play, there should be another bandwidth amplification.

We do not know overall bandwidth efficiency upgrades. But summing all up together it could be on par with RDNA3 + 32 MByte MALL or at least close to it. AT4 could reach N44 performance levels.

• RX 9060 XT has 320 GB/s memory bandwith
• RX 9060 has 288 GB/s memory bandwith
• 128bit LPDDR5X with 8.5 Gbps yields in 171 GB/s 136 GB/s
• 128bit LPDDR5X with 9.6 Gbps yields in 192 GB/s 153 GB/s
• 128bit LPDDR5X with 10.7 Gbps yields in 214 GB/s 171 GB/s
• 128bit LPDDR5X with 12.7 Gbps yields in 254 GB/s 203 GB/s
• 192bit LPDDR6 with 10.67 Gbps yields in 284 GB/s 228 GB/s (effective) --> probably enough bandwidth for a desktop grade part with high clock rates (AMD should have designed / dimensioned it that way)
• 192bit LPDDR6 with 12.8 Gbps yields in 340 GB/s 274 GB/s (effective)

9.6 Gbps bandwidth for a mobile part might be a little bit tight. That is true. But as I said, we simply do not know RDNA5's overall bandwidth efficiency. Maybe LPDDR6 bandwidth levels are plenty enough and LPDDR5X is then sufficient for mobile parts with restricted TDPs. If 12.7 Gbps LPDDR5X gets used (but this memory is probably too expensive and not used), there should be no big difference in bandwidth compared to 10.67 Gbps LPDDR6.

Edit: Corrected bandwidth numbers
https://forums.anandtech.com/threads/zen-6-speculation-thread.2619444/page-363#post-41571222

 

[MerryCherry]

Well, Intel is supposedly not going to use LPDDR6 until Titan Lake in 2029, so AMD isn't doing worse than their immediate competitor in this regard.

 

[Joe NYC]

No way man, that requires a separate platform basically.
QCOM X2ee is a meme part for a reason.

While it may be a meme part, it goes into the same socket.

 

[Joe NYC]

My point has already been rendered moot since it sounds like LPDDR6 is off the table for Medusa Premium laptops. I'm curious why you think that though. Medusa Premium could use 60mm^2 less die area from removing the iGPU, and have simpler and cheaper motherboards and heatsinks.

There would first have to be a new socket that's equivalent to FP10, which will LPDDR6 instead of LPDDR5. LPDDR6 would make it 192 bit wide.

AMD is skipping that for now and jumping to 384 bit wide LPDDR6 socket for Medusa Halo, which will compete with discrete.

 

[adroc_thurston]

While it may be a meme part, it goes into the same socket.

It does not, it's a separate package.

 

[Joe NYC]

It does not, it's a separate package.

You mean differently put together package? Clearly, but it should use the same pinout, same socket.

 

[adroc_thurston]

You mean differently put together package? Clearly, but it should use the same pinout, same socket.

Package == socket in mobile in case you forgot.

 

[Joe NYC]

The really funny thing would be if AT4 was compatible with the MDSH SoC tile.

@Kepler_L2 said different SoCs.

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The reason I think he is right is that Medusa Premium is just going to FP10 socket.

But Medusa Halo will be a new socket, and AMD will turn it into local AI inference monster (as an optional use case). Which would mean significantly upgrading the IO to make it possible to connect several of them together with fast networking or to a fast switch.