Question Zen 6 Speculation Thread

[Covfefe]

According to JEDEC, LPDDR6-14400 has 2x the bandwidth of LPDDR5X-9600. https://www.jedec.org/sites/default/files/Brett Murdock_FINAL_Mobile_2024.pdf

Extrapolating from that. A 192-bit LPDDR6 memory bus has 1.33x the bandwidth of a 128-bit LPDDR5/X memory bus of the same per-pin speed.

A LPDDR6-10667 192-bit config (which should be the base LPDDR6 config for laptops) has 89% as much bandwidth as Strix Halo.

 

[MerryCherry]

A 192 bit LPDDR6 bus nets 227.56 GB/s.

Yes, that's 89% of STXH's 256 GB/s.

So Medusa Halo with 384 bit will have 455 GB/s. A 77% increase.

 

[adroc_thurston]

A LPDDR6-10667 192-bit config (which should be the base LPDDR6 config for laptops) has 89% as much bandwidth as Strix Halo.

see issue is it gotta be FP10, which means 128b L5x only.

 

[MerryCherry]

see issue is it gotta be FP10, which means 128b L5x only.

When will this Medusa premium part release?

I heard Medusa Halo will be CES 2028, so there the time will be ripe for LPDDR6 adoption.

Android flagships with LPDDR6 are slated to debut in 2026Q4, and those will probably be the only consumer devices with LPDDR6 throughout 2027.

 

[adroc_thurston]

When will this Medusa premium part release?

I heard Medusa Halo will be CES 2028, so there the time will be ripe for LPDDR6 adoption.

This has absolutely nothing to do with mem timelines and everything to do with socket pinouts.
FP10 is DDR5/LPDDR5 socket.

 

[Tuna-Fish]

If the part has a combo PHY, I would assume AMD would come out with some new socket for it to use the better RAM. Possibly not at initial release, if LPDDR6 is still very expensive.

I would not take leaks that the Medusa Premium supports FP10 as proof that it only supports it.

 

[adroc_thurston]

If the part has a combo PHY, I would assume AMD would come out with some new socket for it to use the better RAM. Possibly not at initial release, if LPDDR6 is still very expensive.

I would not take leaks that the Medusa Premium supports FP10 as proof that it only supports it.

oh they're definitely gonna stuff it into the halo socket (the gutted 128b stxH SKU exists), but that's memey.
The point is very much stuffing discrete compete into commodity sockets.

 

[marees]

That's not how it works. Both of the combo PHYs announced so far keep the amount of channels constant between the memory types, not the width of the interface. Because all the lines other than data lines would need to be increased for more channels, and you'd have to do weird remapping between data lines of adjacent channels for different widths. (Also, because of changes in how LPDDR6 works, a wider bus is cheaper with LPDDR6 than with LPDDR5X.) A device using such a combo PHY that supports 192-bit LPDDR6 can only support 128-bit LPDDR5X.

so if I understood this correctly the medusa premium in a FP10 socket is restricted to 128bit lpddr5x but in a different (strix halo like) socket, it can go to 192 bit lpddr6 ?

for the AT4 based 10050xt, AMD would have the option of both 128 bit lpddr5x & 192 bit lpddr6 ??

 

[adroc_thurston]

so if I understood this correctly the medusa premium in a FP10 socket is restricted to 128bit lpddr5x but in a different (strix halo like) socket, it can go to 192 bit lpddr6 ?

yes.

for the AT4 based 10050xt, AMD would have the option of both 128 bit lpddr5x & 192 bit lpddr6 ??

also yes. but no, DT one needs all the membw they can muster.

 

[branch_suggestion]

oh they're definitely gonna stuff it into the halo socket (the gutted 128b stxH SKU exists), but that's memey.
The point is very much stuffing discrete compete into commodity sockets.

The really funny thing would be if AT4 was compatible with the MDSH SoC tile.

 

[adroc_thurston]

The really funny thing would be if AT4 was compatible with the MDSH SoC tile.

you mean the MID?

 

[branch_suggestion]

you mean the MID?

Whatever it is called yeah.

 

[adroc_thurston]

Whatever it is called yeah.

Yeah?
AMD hates spending tapeouts on stuff.