Question Zen 6 Speculation Thread

[Joe NYC]

Why not on both sides for cache galore?

So it's 48MB L3 in one plane and only 2*64MB underneath the whole CCD area (L3+12 cores)?
Doesn't seem logical or am I missing something...

Edit: correction

AMD likes to use 4MB L3 on CCD die and 8 MB on V-Cache die. Which will result in Zen 6 with 12 cores having 48MB + 96 MB = 144 MB of L3

If there were to be another layer of L3, it would likely be identical V-Cache die with 96 MB of SRAM.

 

[DrMrLordX]

Why not on both sides for cache galore?

Thermals, and also you're adding even more L3 latency (albeit maybe not that much more).

 

[Doug S]

They are not. The DQ pins are not the only pins on the interface. LPDDR5X has 72 active signals per 32-bit dual channel controller, while LPDDR6 has 84 active signals per 48-bit dual channel (4x half channel) interface. 3/2 data signals but only 7/6 times the pins. Or, 96-bit LPDDR6 uses only 168 signals, while 96-bit LPDDR5X uses 216. Even after you adjust for the 8/9 loss of efficiency from sharing the DQ pins, LPDDR6 comes out ahead.

LPDDR6 is a neat and efficient design.

Wow I didn't realize they'd economized on the pins so much. Will that efficiency help the physical size of an LPDDR6 only controller vs the equivalent width of LPDDR5X only controllers, or just shoreline? I'm guessing Synopsys probably doesn't have LPDDR6 only IP yet to directly make such a comparison. Or do they?

 

[adroc_thurston]

So it's 48MB L3 in one plane and only 2*64MB underneath the whole CCD area (L3+12 cores)?

It's 48M + 96M cache extension.

 

[Tuna-Fish]

Wow I didn't realize they'd economized on the pins so much. Will that efficiency help the physical size of an LPDDR6 only controller vs the equivalent width of LPDDR5X only controllers, or just shoreline? I'm guessing Synopsys probably doesn't have LPDDR6 only IP yet to directly make such a comparison. Or do they?

Yeah, I'm not aware of any apples-to-apples comparisons. I would assume that LPDDR6 PHYs need to be a bit bigger on old process tech, because the CA signals are driven at full speed so there are more high-speed single-ended pins, but I'm really not sure. The controllers are probably a bit bigger because they are probably doing more things.

 

[MoistOintment]

That would certainly be a dream for AMD if they managed to sucker Intel into L3 size competition, where AMD would be stacking cheaper dies with low latency SRAM, while Intel is ballooning the N2 die size and increasing latency.

I imagine Intel's goal is to eventually stack the cache, but they needed a large L3 sooner than they could implement stacking

 

[adroc_thurston]

I imagine Intel's goal is to eventually stack the cache, but they needed a large L3 sooner than they could implement stacking

Intel HBI yields are just too toilet-tier so client guys bailed out.
The OG NVL POR had the cacheslab as eLLC (same as AMD V$).

 

[OneEng2]

I imagine Intel's goal is to eventually stack the cache, but they needed a large L3 sooner than they could implement stacking

Is there any AMD patent that would prevent them from doing that? Since the process is being done at TSMC, it is possible that AMD has exclusive rights to the process at TSMC for some time window as well which would force Intel to either wait for the time window to expire, or implement it on their own (already troubled) process.

 

[adroc_thurston]

Is there any AMD patent that would prevent them from doing that? Since the process is being done at TSMC, it is possible that AMD has exclusive rights to the process at TSMC for some time window as well which would force Intel to either wait for the time window to expire, or implement it on their own (already troubled) process.

No they don't, and Intel stacks caches for CWF/DMR anyway.
It's just their hybrid bonding yield sucks, so client guys NOPE'd out of eLLC in favour of normal 2D slab.

 

[Joe NYC]

Is there any AMD patent that would prevent them from doing that? Since the process is being done at TSMC, it is possible that AMD has exclusive rights to the process at TSMC for some time window as well which would force Intel to either wait for the time window to expire, or implement it on their own (already troubled) process.

Intel and AMD also have a patent cross license agreement.

 

[adroc_thurston]

Intel and AMD also have a patent cross license agreement.

for x86/amd64, not really anything else.

 

[LightningZ71]

I have to wonder if thermals were also an issue for Intel client. It STILL looks like Intel needs to pull a lot of juice to hit their performance targets and I have to wonder if they could reliably stack cache at the thermal loads required for their Fmax targets?

 

[adroc_thurston]

I have to wonder if thermals were also an issue for Intel client. It STILL looks like Intel needs to pull a lot of juice to hit their performance targets and I have to wonder if they could reliably stack cache at the thermal loads required for their Fmax targets?

Relaxing the PT a bit for stacked parts is pretty easy.
Also they did build PVC and are doing CWF et al so they're familiar with thermals in 3D at least.

 

[Doug S]

Is there any AMD patent that would prevent them from doing that? Since the process is being done at TSMC, it is possible that AMD has exclusive rights to the process at TSMC for some time window as well which would force Intel to either wait for the time window to expire, or implement it on their own (already troubled) process.

If there are any patent issues, wouldn't TSMC patents be more likely the hurdle - at least in the future when Intel wishes to reduce reliance on TSMC fabs?

 

[Schmide]

for x86/amd64, not really anything else.

Oh so all the cache, bus, branch prediction, etc is chopped liver ?

 

[adroc_thurston]

Oh so all the cache, bus, branch prediction, etc is chopped liver ?

Buses are an industry thing; rest yeah.
AMD BP in particular is a completely bespoke thingy.

 

[Joe NYC]

It is always an exact match since they moved to wafer on wafer stacking.

BTW, strange that AMD never announced it (as far as I know), nobody asked in any interview.

Last time Max from High Yield did a video on this, he only speculated, and his conclusion was that AMD is still not using Wafer on Wafer packaging, and still using intermediate step of using carrier wafers.

 

[OneEng2]

I have to wonder if thermals were also an issue for Intel client. It STILL looks like Intel needs to pull a lot of juice to hit their performance targets and I have to wonder if they could reliably stack cache at the thermal loads required for their Fmax targets?

Good point. It's currently stacked on top correct?

 

[adroc_thurston]

BTW, strange that AMD never announced it (as far as I know), nobody asked in any interview.

Pretty sure someone (maybe Cheese) did and they pokerfaced it.

Last time Max from High Yield did a video on this, he only speculated, and his conclusion was that AMD is still not using Wafer on Wafer packaging, and still using intermediate step of using carrier wafers.

AMD doesn't do "intermediate steps", they drive the goddamn roadmap at TSMC.

 

[Joe NYC]

Pretty sure someone (maybe Cheese) did and they pokerfaced it.

AMD doesn't do "intermediate steps", they drive the goddamn roadmap at TSMC.

If that's the case, then there should further proliferation of V-Cache CPUs. With Zen 6, V-Cache die will have higher utilization of the V-Cache die, with 96MB on roughly the same die as 64MB on Zen 5.

From the recent presentations, looks like 12 core CCD models will likely have it, 32 core CCD models will likely not have it. Competing with AMD in server space will so much harder.

 

[gdansk]

If they don't have X3D "available" at launch it'll be disappointing

 

[adroc_thurston]

If that's the case, then there should further proliferation of V-Cache CPUs

It means they get higher margins and you get uhhh.

Competing with AMD in server space will so much harder.

you have no idea the nightmares about to happen.

 

[jpiniero]

you have no idea the nightmares about to happen.

AI all the things?

 

[adroc_thurston]

AI all the things?

no, it's just the exterminator.
good against Xeon. good against Neoverse rodents too.

 

[Joe NYC]

It means they get higher margins and you get uhhh.

you have no idea the nightmares about to happen.

I wonder how much there is to this:
- Subtweet: A comment on competitiveness of Arm vs. x86, especially in orchestrating GPU tasks to improve GPU utilization
- Substack article about hyperscalers vertical integration ability to compete with Merchant silicon in both CPU and GPU

https://twitter.com/x/status/2022502484749746436