Question Zen 6 Speculation Thread

[Doug S]

Or A14P might be more appropriate. But since SPR yields a bit better density, A12 could indeed work.

Well I assume the A14P name has been "reserved" for the inevitable optical shrink node like we saw with N7P, N5P, N3P and N2P. I think they chose A16 for N2P+BSPDN rather than calling it something like N2PB to highlight the improved density (even though the density gain is sort of an "it depends" on wire routing conflicts rather than a fairly specific amount as with the 'P' variant optical shrinks)

So if I had to bet I'd guess we'll see the backside variant called A12 rather than something like A14B.

 

[basix]

Nvidia is reportedly the "first and only customer" for A16.

Only customer for now, sure. It depends on time schedules. A16 might just fall in a window, where AMD could choose differently:
- Zen 6 is ~N2P
- MI400 and MI500 are ~N2P/X
- Zen 7 and MI600 will hit the market 2028
- A14 is projected to arrive 2028
- A14 with SPR (super power rail) is projected to arrive 2029

A14 is not that much better than A16 regarding performance and energy efficiency, but it brings additional area scaling benefits.
AMD could still chose A16 for Zen 7 and MI600. But they might not have made the decision yet.

 

[marees]

Only customer for now, sure. It depends on time schedules. A16 might just fall in a window, where AMD could choose differently:
- Zen 6 is ~N2P
- MI400 and MI500 are ~N2P/X
- Zen 7 and MI600 will hit the market 2028
- A14 is projected to arrive 2028
- A14 with SPR (super power rail) is projected to arrive 2029

A14 is not that much better than A16 regarding performance and energy efficiency, but it brings additional area scaling benefits.
AMD could still chose A16 for Zen 7 and MI600. But they might not have made the decision yet.

chips fabricated on BPD/BSPDN inevitably become HPC chips that mandatorily require liquid cooling.

using a BSPDN-enabled node to fabricate a chip dramatically increases design complexity

https://twitter.com/x/status/2017809609474601145

 

[adroc_thurston]

chips fabricated on BPD/BSPDN inevitably become HPC chips that mandatorily require liquid cooling.

using a BSPDN-enabled node to fabricate a chip dramatically increases design complexity

This is both extra stupid and extra wrong.
You can go buy PTL and it's normal client stuff with backside power.

 

[MerryCherry]

This is both extra stupid and extra wrong.
You can go buy PTL and it's normal client stuff with backside power.

Isn't there a difference in the way Intel and TSMC implement BSPD?


Intel uses PowerVia. TSMC uses BSCON.

 

[adroc_thurston]

Isn't there a difference in the way Intel and TSMC implement BSPD?

View attachment 137729
Intel uses PowerVia. TSMC uses BSCON.

There's absolutely zero difference with regards to thermals.
They're the exact same heat traps with pdn water sitting on top of your logic stack.

 

[OneEng2]

TSMC is a foundry and must meet the deadlines promised to its customers. That is why TSMC takes as few risks as possible and avoids introducing two new technologies at once.


BSPDN can only be used if the chip is very well cooled. BSPDN is not suitable for applications without active cooling.

TSMC itself says that BSPDN was designed for HPC. And some say that A16 was developed for Nvidia.

With AMD's "Server First" design approach, seems like BSPDN might work well for DC and AI chips. Might be good enough to justify the hit in desktop since it might ALSO work well for mobile (really any application where lower power outweighs higher clock speeds).

A16 is BSPDN only. A14 will have BSPDN and non BSPDN flavors, though it is unclear if they will share the same A14 name, or the BSPDN version will be called something like A12 similar to how N2P+BSPDN was rebranded as A16.

Thanks for the correction. A16 BSPDN looks like N2 with BSPDN. I agree. Seems like they might want to call the next gen A14 and A12 ..... just due to the likely density difference. It's a harder call though IMO since it is likely that N2 will clock higher than A16 and that A14 will clock higher than A12.

There's absolutely zero difference with regards to thermals.
They're the exact same heat traps with pdn water sitting on top of your logic stack.

There are other difference that may well effect yields and clock speeds.

 

[DavidC1]

Isn't there a difference in the way Intel and TSMC implement BSPD?

Yes, but regardless the power delivery contacts are on the opposite side compared to the general circuitry whichever way you implement that.

 

[fastandfurious6]

Prophecy #212: by the time we reach 1nm proper, computing will be a resolved problem

 

[Thunder 57]

Prophecy #212: by the time we reach 1nm proper, computing will be a resolved problem

Why not make a new thread like you did in the Grapics subforum. For starters how do you even define 1nm proper? Does 18A count? Without quantum computing breaking (certain) encryption simply isn't feasable. But honestly other than specialised tasks like that which have been proven to be possible most people seem to overestimate what quantum computing may bring.