Question Zen 6 Speculation Thread

[Makaveli]

maybe not on the discrete gpu (50xt)

but the medusa premium is like a mini strix halo. you see halo NUCs selling with 128gb unified ram. likewise the medusa premium NUCs (with the 50xt attached) will also come with atleast 64gb unified RAM

100% agreed for non discrete gpu's

 

[basix]

You think like a consumer.
"2x gaming perf" is not a thing without doubling the SoC power anyway.

I think like a consumer, yes. And I, the almighty consumer (aka king), will make the buying decision Intel vs. AMD 😉

And as I said, use less CU but at least get other benefits like improved DNN acceleration.

Basic engineering principle "You don't get something for nothing".

Sure. But porting RDNA 3.5 to N3P is effort as well. RDNA5 is natively designed for N3P.

The most logical reason to use RDNA 3.5 is simply: Timelines.
RDNA5 might just not be ready for prime time yet when Medusa Point shall get released. Timeline was also one major reason for using Vega that long.
But if timelines are not matching for RDNA5, RDNA4 is out in the wild since early 2025...

 

[adroc_thurston]

I think like a consumer, yes. And I, the almighty consumer (aka king), will make the buying decision Intel vs. AMD 😉

OEMs will guide you the right way.
In any case, everything depends on MDS 1t/BL, and not

And as I said, use less CU but at least get other benefits like improved DNN acceleration.

This part was made before GPU guys won.

 

[LightningZ71]

What I'm wondering is, in the poverty class that keeps the RDNA 3.5 iGPU, does it keep a separate NPU? I have to wonder if it makes sense to have to port both to N3 class nodes instead of just using RDNA 5 that's already going to be ported there, or is it a timeline issue for RDNA 5?

 

[adroc_thurston]

What I'm wondering is, in the poverty class that keeps the RDNA 3.5 iGPU, does it keep a separate NPU?

Yeah.

I have to wonder if it makes sense to have to port both to N3 class nodes instead of just using RDNA 5 that's already going to be ported there, or is it a timeline issue for RDNA 5?

Separate programs with separate schedules.

 

[Kepler_L2]

https://twitter.com/x/status/2017245821738316188

 

[OneEng2]

A14 is wholly unrelated to N2.

Lithography: Same
GAA: Same
Low NA: Same (both use mult-patterning instead)
BSPDN: No (Same)

What IS potentially different?

• More granular drive strength options in libraries
• More granular block libraries (enhance NanoFlex capabilities)
• Tweaked and tightened transistor libraries.

Sure, TSMC wants to call this a new node. They get to charge more that way. I don't want to belabor the point, but tweaking libraries to ME doesn't justify calling it a new node. It's just a tweak.

We will see bigger jumps with High NA and again with BSPDN. Those both justify calling it a new node in my book. YMMV.

 

[511]

https://twitter.com/x/status/2017245821738316188

You beat me to it lol

Lithography: Same
GAA: Same
Low NA: Same (both use mult-patterning instead)
BSPDN: No (Same)

What IS potentially different?

• More granular drive strength options in libraries
• More granular block libraries (enhance NanoFlex capabilities)
• Tweaked and tightened transistor libraries.

Sure, TSMC wants to call this a new node. They get to charge more that way. I don't want to belabor the point, but tweaking libraries to ME doesn't justify calling it a new node. It's just a tweak.

We will see bigger jumps with High NA and again with BSPDN. Those both justify calling it a new node in my book. YMMV.

Uhh High Na is about reducing the multi patterning to single patterning multiple pass to single pass there are still challenges with Hign-Na Litho first and foremost the ecosystem being not mature enough

 

[OneEng2]

You beat me to it lol

Uhh High Na is about reducing the multi patterning to single patterning multiple pass to single pass there are still challenges with Hign-Na Litho first and foremost the ecosystem being not mature enough

High NA is about having the ability to image smaller aspects than Low NA and make smaller traces.

Yes, it is possible that High NA could simply be used to make the same trace width as Low NA multi-pass, but it is much more likely that it will be used WITH multi-pass to make smaller traces and a higher transistor density.

This is how I understand it. Someone correct me if I am missing something.

 

[marees]

Linux driver for AMD Medusa XDNA NPU (AIE4) was already submitted on GitHub last month, and some details like SR-IOV support have also been made public.

https://twitter.com/x/status/2017197402881679780

AMD XDNA Driver Update Unveils NPU3A Silicon and Strategic Shift Towards Linux Upstreaming

Blog com notícias sobre, Linux, Android, Segurança , etc

portallinuxferramentas.blogspot.com

 

[itsmydamnation]

High NA is about having the ability to image smaller aspects than Low NA and make smaller traces.

Yes, it is possible that High NA could simply be used to make the same trace width as Low NA multi-pass, but it is much more likely that it will be used WITH multi-pass to make smaller traces and a higher transistor density.

This is how I understand it. Someone correct me if I am missing something.

so its 13nm for EUV and 8nm for High NA. but the interesting thing is beam width is not the limiting factor for EUV, stochastic defects become a problem bellow ~32nm. I can find no good public reference on the behaviour for High NA( honnestly didnt try that hard) , so how it will be used is hard to tell, it might be a big enough jump that you can get a feature size reduction even with a single pass.

im guessing something like this is probably heapfull in understanding

https://www.spiedigitallibrary.org/conference-proceedings-of-spie/13216/1321604/Logic-and-memory-patterning-breakthrough-using-High-NA-lithography/10.1117/12.3047176.short

 

[Doug S]

High NA is about having the ability to image smaller aspects than Low NA and make smaller traces.

Yes, it is possible that High NA could simply be used to make the same trace width as Low NA multi-pass, but it is much more likely that it will be used WITH multi-pass to make smaller traces and a higher transistor density.

This is how I understand it. Someone correct me if I am missing something.

High NA EUV machines cost over 2x as much and have lower wph throughput. It costs a lot more to do a single high NA EUV pass than it does to do two standard EUV passes. It isn't far from the cost of THREE standard EUV passes.

You can get the same feature size either way. Just like TSMC used multipass DUV to do N7 and then later used single pass EUV in a few layers instead of the multiple DUV passes. Now OK sure you can do multiple passes with high NA EUV to get smaller feature sizes than standard EUV is capable of. But the cost of those nodes would be insane.

If you want more density another way to get there is CFET which has transistors that take up less area because the components are stacked even moreso than GAA transistors. But that isn't dependent on lithography, it is primarily dependent on a lot more etch and deposition passes.

 

[OneEng2]

High NA EUV machines cost over 2x as much and have lower wph throughput. It costs a lot more to do a single high NA EUV pass than it does to do two standard EUV passes. It isn't far from the cost of THREE standard EUV passes.

You can get the same feature size either way. Just like TSMC used multipass DUV to do N7 and then later used single pass EUV in a few layers instead of the multiple DUV passes. Now OK sure you can do multiple passes with high NA EUV to get smaller feature sizes than standard EUV is capable of. But the cost of those nodes would be insane.

If you want more density another way to get there is CFET which has transistors that take up less area because the components are stacked even moreso than GAA transistors. But that isn't dependent on lithography, it is primarily dependent on a lot more etch and deposition passes.

I don't know about 2x as much, but you might be right (I don't buy lithography machines 😉 ).

Still, my point is that there isn't a huge difference between N2 and A14 (20% density, 30% power at same clock). Nearly all of these gains are likely due to the move to BSPDN. AMD will likely wait out A14 for Zen 7 putting it out into 2028 (which makes sense considering AMD's most recent cadence). Zen 6 is going to spend lots of time being the top dog in the AMD arsenal IMO.

Now, I originally stated "No BSPDN" which I believe is incorrect. This does make A14 quite a different technology from N2 IMO. It will be interesting to see if any products are built on the BSPDN version of A16 and how those perform relative to the non BSPDN version.

I remain concerned about all the traditional issues with BSPDN that can limit yields and cause clock bottlenecks at hot spot areas (which I am sure Intel are now learning all about). According to what I can find though, at A14 things may become limited by the FSP I2R losses completely without BSPDN.... so ..... physics strikes again.

 

[adroc_thurston]

Nearly all of these gains are likely due to the move to BSPDN

A14 does not have backside power by default.
It has a variant with that.

 

[OneEng2]

A14 does not have backside power by default.
It has a variant with that.

My bad. You appear to be correct.

So both A16 and A14 will be split. Interesting. My guess is that TSMC is having their doubts about the technologies readiness for HVM in all applications.

I still wonder if it won't be a good fit for high core count DC where PPA is way more important than max clocks and max single threaded performance (like client).

 

[basix]

Linux driver for AMD Medusa XDNA NPU (AIE4) was already submitted on GitHub last month, and some details like SR-IOV support have also been made public.

AMD recently also showed AIE4ML, a framework / tool chain for compiling DNN into optimized AIE-ML/AIE-MLv2 code:

AIE4ML: An End-to-End Framework for Compiling Neural Networks for the Next Generation of AMD AI Engines

Efficient AI inference on AMD's Versal AI Engine (AIE) is challenging due to tightly coupled VLIW execution, explicit datapaths, and local memory management. Prior work focused on first-generation AIE kernel optimizations, without tackling full neural network execution across the 2D array. In...

arxiv.org

 

[Kaffeekenan]

Anyone who knows 2026/2027 server comp positioning would tell you that.

yes it sucks a fat one.

well, pay me, and I'll tell you.

uh, no, GPU tiling is a win-more scenario.
It's not cost-effective to build GPUs with tiling since SoIC-X d2w costs + AID per config make it unviable.

they need the shills. and the choppa. they have neither; thus they're dead.

Hmm, @adroc_thurston, can you get just a little bit more specific about DMR? "It sucks a fat one" can kinda mean anything. What ist the main problem with it? Or the main advantage of Zen 6 compared to DMR in your opinion. Please try to be a little bit specific and try not to answer "AMD cores go BRRRRRRRRR" or something like that...because honestly that is something even I could write. :-D

 

[adroc_thurston]

"It sucks a fat one" can kinda mean anything

It means it sucks a fat one.
Simple enough?

What ist the main problem with it? Or the main advantage of Zen 6 compared to DMR in your opinion.

Perf. DMR perf sucks.

Please try to be a little bit specific and try not to answer "AMD cores go BRRRRRRRRR" or something like that...because honestly that is something even I could write.

It's quite literally what's happening.
It's the first Actually Expensive EPYC which bears appropriate implicatitons.

 

[DrMrLordX]

Hmm, @adroc_thurston, can you get just a little bit more specific about DMR? "It sucks a fat one" can kinda mean anything. What ist the main problem with it? Or the main advantage of Zen 6 compared to DMR in your opinion. Please try to be a little bit specific and try not to answer "AMD cores go BRRRRRRRRR" or something like that...because honestly that is something even I could write. :-D

I am not he, but the fact that Intel cancelled Diamond Rapids-SP ought to tell you something.

 

[adroc_thurston]

but the fact that Intel cancelled Diamond Rapids-SP ought to tell you something.

Moreover, the official reason is accelerating Coral which tells you just about *everything* you gotta know about DMR perf.

 

[ETI4711]

So both A16 and A14 will be split. Interesting. My guess is that TSMC is having their doubts about the technologies readiness for HVM in all applications.

TSMC is a foundry and must meet the deadlines promised to its customers. That is why TSMC takes as few risks as possible and avoids introducing two new technologies at once.


BSPDN can only be used if the chip is very well cooled. BSPDN is not suitable for applications without active cooling.

TSMC itself says that BSPDN was designed for HPC. And some say that A16 was developed for Nvidia.

 

[adroc_thurston]

TSMC itself says that BSPDN was designed for HPC. And some say that A16 was developed for Nvidia.

The OG N2 BSPDN variant was built for AMD.

 

[Doug S]

My bad. You appear to be correct.

So both A16 and A14 will be split. Interesting. My guess is that TSMC is having their doubts about the technologies readiness for HVM in all applications.

I still wonder if it won't be a good fit for high core count DC where PPA is way more important than max clocks and max single threaded performance (like client).

A16 is BSPDN only. A14 will have BSPDN and non BSPDN flavors, though it is unclear if they will share the same A14 name, or the BSPDN version will be called something like A12 similar to how N2P+BSPDN was rebranded as A16.

 

[Doug S]

TSMC itself says that BSPDN was designed for HPC. And some say that A16 was developed for Nvidia.

Nvidia is reportedly the "first and only customer" for A16.

 

[jdubs03]

A16 is BSPDN only. A14 will have BSPDN and non BSPDN flavors, though it is unclear if they will share the same A14 name, or the BSPDN version will be called something like A12 similar to how N2P+BSPDN was rebranded as A16.

Or A14P might be more appropriate. But since SPR yields a bit better density, A12 could indeed work.