Question Zen 6 Speculation Thread

[maddie]

To the group, isn't Venice dense looking like a huge chiplet?

 

[adroc_thurston]

To the group, isn't Venice dense looking like a huge chiplet?

Does it matter?
CSPs can and will pay.

 

[maddie]

Does it matter?
CSPs can and will pay.

True.

 

[Joe NYC]

To the group, isn't Venice dense looking like a huge chiplet?

Maybe ~200 mm2? Could be below that.

 

[techjunkie123]

To the group, isn't Venice dense looking like a huge chiplet?

My estimate is ~150 mm^2. Pretty manageable.

Source: trustmebro™

 

[reaperrr3]

Assuming that will be the case, why will they choose different policy for Zen6 vs Zen5? Why use different nodes per CPU type for Zen5 but not for Zen6? I assume there was some reason different nodes were used for Zen5.

That's not hard to guess or explain, and the only reason we're still having this discussion at all is because some people refuse to accept the reasons and explanations that have been given multiple times.

In short, Zen5 was mostly an outlier because TSMC messed up the original N3.

It also was actually an all-N4P gen (with some 'X' transistors in the 8C CCD, allegedly), except one single N3E CCD, for a possibly area-constrained* product in a very high-margin market niche, where any cost/yield issues would've been relatively easy to absorb.

*Turin-D has 12 CCDs, and look at that package layout.
You think they could've fit those 12 CCDs on that if these CCDs were ~30% bigger?
Tricky at best, impossible at worst.

 

[adroc_thurston]

You think they could've fit those 12 CCDs on that if these CCDs were ~30% bigger?

Yeah.
It's on N3e for PPW buffs and also via being the least important product ever.

 

[Josh128]

Found this page at TSMCs website. I found this by doing a google search on differences between TSMC standard and HPC processes. Usually,
standard vs HPC means tradeoffs in density and/or leakage. It appears that there is little performance difference, and therefore presumably little density and
leakage differences, between N2P and N2.

Advanced Technologies for HPC - Taiwan Semiconductor Manufacturing Company Limited

N5 is the next-generation technology after N7 that is optimized upfront for both mobile and HPC applications. It is defined with innovative scaling features to enhance logic, SRAM and analog density simultaneously. Compared with N7, N5 offers substantial power, performance and date density...

www.tsmc.com