Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Philste]

Figure people who are buying Intel Servers are buying Emerald.

I think Diamond Rapids is a new socket again, so Granite Rapids is in a kinda awkward position. Sierra Forest at least has one successor for it's Socket.

 

[Joe NYC]

I think Diamond Rapids is a new socket again

Seriously? I thought it would continue in the same socket as Sierra Forest and Grand Rapids.

That's bad...

 

[Geddagod]

Interestingly enough, at Dell and Lenovo it doesn't appear you can buy a Granite Rapids server. There is one Sierra Forrest server but dunno if people are buying that. Meanwhile I think I saw multiple Zen 5.

Figure people who are buying Intel Servers are buying Emerald.

GNR appears to have a pretty slow ramp/volume issues.

Seriously? I thought it would continue in the same socket as Sierra Forest and Grand Rapids.

That's bad...

Not only is it rumors, I think Gelsinger even confirmed it in an earnings call or some tech conference (some off hand remark about DMR using a new platform) a while back. I couldn't dig it up from a short search so I may be misremembering though.

 

[Geddagod]

If you slow down

(they provide the timestamps) Zen 5 related part, you are able to read all the slides. Since I was unable to listen in at the time, I haven't listened to their comments.

Funny thing AMD downgraded Zen4 FPU to be 3 wide for the purposes of this comparison, since this is mentioned twice on different slides, I doubt it's just a type. So either someone did not read the Zen4 software optimization manual, or that manual was not telling the full story.

Some interesting stuff IMO:
AMD confirms Zen 5 power cross over point with Zen 4, once again I should mention this was not mentioned for the Zen 3 to Zen 2 jump. I really do believe whatever magic sauce AMD had with the Zen 3 jump was not present with the Zen 5 jump.
Majority of 8T SRAM is now moved to 6T SRAM, in order to reduce area. Given the large jump in structure capacity in Zen 5 vs Zen 4, this makes sense.
Zen 4 ring > Zen 5 mesh. Adored's zen 5 ladder cache stuff seems to have been true. Core to core latency within the same CCD vs Zen 4 seems to have slightly increased.
Increased metal layers with their 4nm node. I tried looking thru amd phoenix paper to see if they talked about it there, but didnt see anything.
STD cell library still HD.

 

[yuri69]

Zen 4 ring > Zen 5 mesh.

They needed something scalable for CCXes having 16 (and probably 32) cores. So this makes sense but having such CCX benchmarked would be great.

 

[sl0519]

https://videocardz.com/newz/amd-ryzen-9-9950x3d-tested-two-weeks-ahead-of-launch-similar-cinebench-performance-to-9950x

V-cache die doesn't seem to be clocked much lower this time?

 

[MS_AT]

V-cache die doesn't seem to be clocked much lower this time?

We do not know if this is an OC result or not. Since it would be 300MHz over stock 9800x3d I won't risk guessing as both options (higher stock clk on better binned parts or OC) could be true.

 

[jdubs03]

In case y’all are interested:

AMD Ryzen AI Max+ 395 Analysis - Strix Halo to rival Apple M4 Pro/Max with 16 Zen 5 cores and iGPU on par with RTX 4070 Laptop

The new Ryzen AI Max+ 395 is AMD's latest high-end mobile processor. With up to 16 Zen 5 cores, a powerful Radeon GPU, fast NPU and up to 128 GB RAM, the Ryzen AI Max+ is supposed to be the ideal companion for gaming, content creation, and AI development.

www.notebookcheck.net

Not too shabby, not too shabby at all. Only complaint is single-core is lacking.
I’d be curious how the 9955X(3D) compares.. on the CPU side.

 

[eek2121]

We do not know if this is an OC result or not. Since it would be 300MHz over stock 9800x3d I won't risk guessing as both options (higher stock clk on better binned parts or OC) could be true.

It’s not. That is stock performance.

 

[MS_AT]

It’s not. That is stock performance.

Is that a gut feeling or you just know based on the reasons you might not discuss? [I am getting lost who here has access to pre-release HW, and so on]

 

[gdansk]

At ISSCC AMD said it has 200 MHz higher boost clock on X3D CCD. That's all folks.

 

[MS_AT]

At ISSCC AMD said it has 200 MHz higher boost clock on X3D CCD. That's all folks.

Well at ISSCC AMD has retroactively removed an execution pipe from all Zen4 chips, so who knows, be wary of BIOS updates lol. (Now, I believe it was just a typo, before somebody on wccftech will make a rumor out of it...)

Still that particular slide might have referred to just to an existing SKU (9800x3d) as I believe it saw the 200MHz gain over Zen 4. Anyway, we will know in 3 weeks.

 

[gdansk]

Still that particular slide might have referred to just to an existing SKU (9800x3d) as I believe it saw the 200MHz gain over Zen 4. Anyway, we will know in 3 weeks.

Nope, at peak. The hopium should have been cut off a while ago.

 

[eek2121]

Is that a gut feeling or you just know based on the reasons you might not discuss? [I am getting lost who here has access to pre-release HW, and so on]

It lines up with some other leaks that have popped up in the past, including the above claim from AMD.

I plan on getting one, but not at release.

 

[StefanR5R]

At ISSCC AMD said it has 200 MHz higher boost clock on X3D CCD. That's all folks.

Still that particular slide might have referred to just to an existing SKU (9800x3d)

The ISSCC presentation was certainly only about products which already had been launched in advance of the ISSCC paper submission date well in advance of ISSCC.
Edit:
– ISSCC paper submission deadline was September 4th.
– AMD revealed the 9800X3D on October 31, review embargos ended on November 6.
– AMD revealed 9950X3D on January 6, review embargos will allegedly end on March 11.

https://videocardz.com/newz/amd-ryz...launch-similar-cinebench-performance-to-9950x

V-cache die doesn't seem to be clocked much lower this time?

The HWinfo screenshot there shows 5.54 GHz peak of cores of the 3D V-Cache CCD and 5.71 GHz peak of cores of the vanilla CCD.
For reference, AMD specifies Ryzen 7 9800X3D's peak boost clock as 5.2 GHz and 7800X3D's as 5 GHz.

 

[gdansk]

The ISSCC presentation was certainly only about products which already had been launched in advance of the ISSCC paper submission date.

It was submitted in August. So I don't think so.
There is no chance that 9950X3D CCD boosts over 5450MHz. Stop the hype train. Stop the hopium, it's over. It's been over. AMD has told us in multiple different ways already but people are still hoping it's better than it is.

The only thing left to speculate about for Zen 5 is the core size of Zen 5c on N3E which AMD hasn't given in any presentation yet.

 

[StefanR5R]

It was submitted in August.

Right, I corrected my post. (Before seeing your response.)

Stop the hopium, it's over.

I for one couldn't care less about (1.) peak boost clocks, (2.) inhomogeneous CPUs.

5450MHz

5450, 5540, same thing. Close enough to the 5.7 of the other CCD.

 

[gdansk]

5450, 5540, same thing

5450 is the best bin likely to exist. It may ship lower. And if they do make a 9950X3D2 it is unlikely it'll have two of the top bins. You will always get heterogeneous (to varying degrees).

 

[adroc_thurston]

You will always get heterogeneous (to varying degrees).

Tiny bit of freq delta is not heterogeneous, otherwise everything from the first multicore CPU shipped is that.

 

[gdansk]

Tiny bit of freq delta is not heterogeneous, otherwise everything from the first multicore CPU shipped is that.

You're right. But these are people who want dual stacked cache CCDs to eliminate heterogeneity. It may be good enough for some niche purposes but there is no reason to add latency for consumer workloads which is what Ryzen targets.

It's not an upgrade for the market which Ryzen targets. And the 9800X3D is still not in stock. Hopes and dreams need to die sometimes.

 

[MS_AT]

There is no chance that 9950X3D CCD boosts over 5450MH

I probably was misunderstood, I meant it would be a success if 5450MHz was possible to reach by x3d chiplet at stock conditions without overclock as that is 200MHz more than what 9800x3d can do at stock and enough for the x3d chiplet to tie the other chiplet in Spec.

 

[Abwx]

The screen shot for the dyslexic :

AMD Ryzen 9 9950X3D CPU Leaked Benchmarks Reveal Ryzen 9950X Equivalent Performance In Synthetic Tests

AMD Ryzen 9 9950X3D was recently tested in multiple synthetic tests, revealing performance equivalent to its non-X3D variant.

wccftech.com

 

[Saylick]

The screen shot for the dyslexic :

AMD Ryzen 9 9950X3D CPU Leaked Benchmarks Reveal Ryzen 9950X Equivalent Performance In Synthetic Tests

AMD Ryzen 9 9950X3D was recently tested in multiple synthetic tests, revealing performance equivalent to its non-X3D variant.

wccftech.com

Thanks. I'm not dyslexic but I don't want to lose brain cells by giving those hacks my clicks.

 

[carrotmania]

I really do believe whatever magic sauce AMD had with the Zen 3 jump was not present with the Zen 5 jump.

Conversely, I'm convinced Zen5 was as good as AMD hoped... when they started its design. The problem for them, which has tainted OUR perception was that Intel actually did have a last hurrah, with the recent Lakes, and both companies realised they would have to push their chips HARD to compete. Zen4, IMO, was pushed way harder than AMD originally intended, to compete with 13/14 series. So much so that it crossed the performance line into plannrd Zen5 territory, a generation earlier. Kinda proof can be seen in how AMD have managed Epyc. Zen5 in that environment is a good 30-50% faster, cos it clocks easier across the board. I dunt think AMD originally wanted their first AM5 chips to instantly draw the full wattage the new socket could provide. But then they wouldn't have been competitive with Intels furnace inducing, self destructing chips. Ho hum.

 

[Geddagod]

Conversely, I'm convinced Zen5 was as good as AMD hoped... when they started its design. The problem for them, which has tainted OUR perception was that Intel actually did have a last hurrah, with the recent Lakes, and both companies realised they would have to push their chips HARD to compete. Zen4, IMO, was pushed way harder than AMD originally intended, to compete with 13/14 series. So much so that it crossed the performance line into plannrd Zen5 territory, a generation earlier.

AMD engineers claimed they under-achieved their Zen 4 Fmax goals. I don't think, unless AMD increased nT power draw for Zen 5 while keeping the all core boost of Zen 4 arbitrarily low, Zen 5 was going to be a large upgrade in traditional nT perf.
I don't think Zen 5 is a bad uplift totally, but it's not on par with what AMD achieved with Zen 3 (core wise). Maybe because their base with Zen 4 was already so good. The Zen 5>Zen 4 PPA uplift seems more in line with Intel's Cove uplifts than Zen 3>Zen 4.
Comparing the GLC vs WLC and the Zen 5 vs Zen 4 uplift is going to be pretty interesting, if anyone can find data on a GLC vs WLC power curve (I have yet to seen anything with this data).

Kinda proof can be seen in how AMD have managed Epyc. Zen5 in that environment is a good 30-50% faster, cos it clocks easier across the board. I dunt think AMD originally wanted their first AM5 chips to instantly draw the full wattage the new socket could provide. But then they wouldn't have been competitive with Intels furnace inducing, self destructing chips. Ho hum.

Zen 5 server also increase core counts and has a new IO die. Idk if that's proof.