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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Timmah! said:
Then the question should be, why thats the case, if some other apps, that utilize 4090, can overflow to system RAM, once the VRAM is filled. Naturally this tanks performance, but maybe thats still better than no performance at all?
Are LLMs latency-sensitive like games?
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Afaik not to latency, but definitely to bandwidth. Besides small (<10B) models no one uses system RAM for LLMs, once you offload to that some parts of a large model, performance tanks very quickly.
 
Kryohi said:
Afaik not to latency, but definitely to bandwidth. Besides small (<10B) models no one uses system RAM for LLMs, once you offload to that some parts of a large model, performance tanks very quickly.
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But its gonna be system RAM, whats gonna be used in case of Halo, no?
 
FlameTail said:
Kraken Point appears in Geekbench

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It looks like a very competitive chips for mainstream market, for laptops less expensive than Strix Point and Lunar Lake.

Performance should be quite close to Strix Point in most typical ST centric applications, and it looks like all 8 cores are on the same ring with 16MB L3, which would improve performance when running on 5c cores (due to larger L3) and cost of switching to full cores should be less. So overall power efficiency vs. Strix Point should go up.

Also, cheapest to manufacture (vs. Strix Point and Lunar Lake).
 
Joe NYC said:
and it looks like all 8 cores are on the same ring with 16MB L3, which would improve performance when running on 5c cores (due to larger L3) and cost of switching to full cores should be less. So overall power efficiency vs. Strix Point should go up.
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Where do you deduce this from? I agree, it would help perf, but up until this point it didnt look that way. I still think either 4C CCX +4C CCX will be more likely. Thats what the Geekbench shows. L3 would not be unified between the two CCXs.

1734102783115.png
 
Josh128 said:
Where do you deduce this from? I agree, it would help perf, but up until this point it didnt look that way. I still think either 4C CCX +4C CCX will be more likely. Thats what the Geekbench shows. L3 would not be unified between the two CCXs.

View attachment 113150
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Just a speculation, based on the fact that AMD can do ring bus with 8 stops.

It would be wasteful if if Kraken had 4x Zen 5c with a separate L3 and it would suck if the Zen 5c cores had no L3. So just connecting some dots (which may turn out to be wrong).
 
Joe NYC said:
Just a speculation, based on the fact that AMD can do ring bus with 8 stops.

It would be wasteful if if Kraken had 4x Zen 5c with a separate L3 and it would suck if the Zen 5c cores had no L3. So just connecting some dots (which may turn out to be wrong).
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Joe, this is AMD we are talking about, AND presumably their lowest profit SKU. They likely just took the Strix design and neutered the Zen 5C 8 core cluster down to 4, cut the GPU down, and otherwise retained the exact same design to save time and money.
 
Josh128 said:
Joe, this is AMD we are talking about, AND presumably their lowest profit SKU. They likely just took the Strix design and neutered the Zen 5C 8 core cluster down to 4, cut the GPU down, and otherwise retained the exact same design to save time and money.
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It's a brand new die, and I think this will be a high volume die for Zen 5. So, it would make sense, for area efficiency, remove the 2nd ring bus and its L3 altogether. And then sell a very area efficient CPU, in order to achieve good margins.

So, some additional design cost in that but lower die costs to offset them. AMD also took extra 6 months for Kracken after Strix Point, which would also point in the direction that AMD took time to get this one right.
 
gdansk said:
It isn't small, apparently.
Rumor says it is slightly larger than Phoenix 1.
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Which would make it bigger than Hamoa die of X Elite.
AMDPhoenix178 mm²
Qualcomm Hamoa172 mm²
Qualcomm Purwa~130 mm²
Josh128 said:
Yes, but it shows two "Clusters", which is accurate. I'd be willing to bet Krakan's cluster setup is the same. High latency coms between cores from differing clusters, just like Strix.
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Geekbench reads that different cores are in different clusters, even if technically they are in the same cluster.
 
Abwx said:
Smaller GPU than HPoint and also 4 Zen 5c cores, so it could eventualy be smaller if it wasnt for the bigger NPU, we can expect a comparable 178mm2 size.
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I don't know if this is the correct scale, but if you remove 8 MB L3 and 4 "c" cores, and also similar reduction to GPU, and if everything else stays the same, it would probably be around 15% reduction:

1734140561123.png
 
It's gonna be a really awkward time point for AMD - in 2025 dGPU designs will go with Ryzen 200 (hawk), and iGPU designs will go for Ryzen 300 (kraken). Considering their die sizes, the cost of ryzen 200 8-core and ryen 300 8-core will be close.
 
SteinFG said:
It's gonna be a really awkward time point for AMD - in 2025 dGPU designs will go with Ryzen 200 (hawk), and iGPU designs will go for Ryzen 300 (kraken). Considering their die sizes, the cost of ryzen 200 8-core and ryen 300 8-core will be close.
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They'll be happy selling units either way. It's up to the OEMs to decide what they want to deliver to customers.
 
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