- Mar 3, 2017
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Indeed,
A single mobile LPDDR6 CAMM2 memory module will max out at ~500 MB/s. That's double the Strix HALO bandwidth or halve the RTX 4090 bandwidth.
Expect beefy iGPU's in the not so far away future.
View attachment 112566
Trinary signaling can transfer 8x32 bit in 7 cycles over a 24 bit bus. At 14.4 GT/s that amounts to 65.8 GB/s. Eight 24 bit busses add up to ~526 GB/s.
No. LPDDR6 is NRZ, and transfers 288 bits over 24 cycles per 12-bit subchannel. Of that, 256 is payload, 16 is host-defined metadata and 16 is either link protection RAS or DBI for power reduction.
At 14.4GT/s a single 192bit LPDDR6 module has a total throughput of 14.4*192/8*(256/288) = 307.2GB/s.
The 24 bit channels, with two 12 bit sub channels do allow both PAM3 and NRZ versions in an efficient manner.
For NRZ only you would simply use bus sizes with powers of 2.
I don't know if they have given up on PAM3 versions already?
PAM3 for LPDDR6 presumably
=========================
2 cycles over one line: 3^2 = 9
9 > 8 (3 bits)
2 cycles over 12 lines: 36 bits
16 cycles over 12 lines: 288 bits
So the PAM3 version would have a 16 cycle burst versus the 24 cycle burst of NRZ.
This gives a maximum bandwith of 460.8 GB/s
The data transfer efficiency is: 256/288 x log(8)/log(9) = 84.12%
The trinary to binary conversion efficiency is: 3/2 x log(2)/log(3) = 94.64%
PAM3 theoretically (very high efficiency version)
======================================
7 cycles over a single line: 3^7 = 2187
2187 > 2048 (11 bits)
7 cycles over 3 lines = 33 bits = 32 + 1 bit
This gives a maximum bandwidth of 526 GB/s
The data tranfer efficiency is: 32/( 3 log(3^7)/log(2)) = 96.14%
The trinary to binary conversion efficiency is: 11/7 x log(2)/log(3) = 99.15%
There maybe will be one later, presumably called LPDDR6X. But LPDDR6 is set in stone, does not use it, and as far as I know, was never planned to use it.The 24 bit channels, with two 12 bit sub channels do allow both PAM3 and NRZ versions in an efficient manner.
For NRZ only you would simply use bus sizes with powers of 2.
I don't know if they have given up on PAM3 versions already?
Bruh. World record?? Be very careful with that 1.4V mate, Anyway, whats the secret to reducing CL? My Teamgroup 6000 30-36-36-76 wont even post if I try to go CL28 without touching anything else from EXPO settings. Does increased RAM voltage help with lower CL? I know it helps with upping freq. Im not looking to break any records, just trying to pick low hanging fruit.
Don't use EXPO. Switch to manual timings and only enter 6000 for speed and 28 for CL and let everything else remain on AUTO. Then the mobo should try to train the memory at that latency. If it fails, then you need to reduce speed to 5800 or even 5600. For a kit that can do CL28 at 6000, it should be rated for 6600 or 6800.My Teamgroup 6000 30-36-36-76 wont even post if I try to go CL28 without touching anything else from EXPO settings.
Inb4 Userbenchmark owner changes how the score is calculated to put Intel back on top.I did it guys im top1 on userbenchmark in memory score
Beat every 14900k and 14900ksView attachment 112710View attachment 112709
Ye he will somehow change my 100% memory score so im below that 8800mt/s 14900ks who i beat xDInb4 Userbenchmark owner changes how the score is calculated to put Intel back on top.
With what CPU/setup?I did it guys im top1 on userbenchmark in memory score
Beat every 14900k and 14900ksView attachment 112710View attachment 112709
You got 34ns memory latency?? Lowest Ive seen for any Zen 5 is in the 50s in AIDA64. Must be reading something differently.9800x3d duuh.
Lol its userbenchmark dude. His numbers mean nothing xDYou got 34ns memory latency?? Lowest Ive seen for any Zen 5 is in the 50s in AIDA64. Must be reading something differently.
UB code loop got stuck in V-cache and kept bouncing aroundYou got 34ns memory latency??
No wonder it's OOS everywhere. It's a legendary CPU, the 9800X3D.
I've read the opposite. It increases the latency because the way AIDA64 calculates the latency doesn't take into account the change they made. Performance in games may be better. If you don't like the change, the BIOS will have a legacy option which resets the behavior back to launch one, according to AMD but they can only provide guidance to their partners. It's up to the mobo maker to decide what to name that option.New AGESA 1.2.0.2.b out that supposedly reduces AIDA64 mem latency figure.
According to WCCFTECH, its the previous 1.2.0.2a patch that increased the way AIDA64 reads it. In any case, their cited source claims BOTH faster gaming AND reduced reported latency in AIDA64. 🤷♂️I've read the opposite. It increases the latency because the way AIDA64 calculates the latency doesn't take into account the change they made. Performance in games may be better. If you don't like the change, the BIOS will have a legacy option which resets the behavior back to launch one, according to AMD but they can only provide guidance to their partners. It's up to the mobo maker to decide what to name that option.
As mentioned in the results, this was achieved via BIOS 3065 Beta, which isn't yet official. Currently, you can only download the BIOS 3057 for this particular model, which comes with the AGESA 1.2.0.2a patch. However, the latest one should come out in a few days. One more thing to point out here is that the 1.2.0.2b patch shows improved memory latency as tested by the user in AIDA64 Extreme. As mentioned in the intro, the memory latency decreased to 64 ns from over 68 ns. This is similar to pre-AGESA 1.2.0.2a patch latency.
Kind of sane. Though I wonder why they didn't go higher. Probably to reduce power consumption.Only 5.1 GHz boost clock speed?
Strix Halo GPU performance leak:
