Yeah, saw it with the RAM types leading up to DDR and then beyond that. I got onto team DDR3 near the very end when they were pushing high speeds out of the fabs. Good times. Hopefully by production year two we'll see some decent speeds. And price. Price is inherent to upgrade paths, and it's one I'd rather not pay out the nose for.
Mind what I said, but I said that in reference to AMD's AM4 launch for Zen. I believe AM4 predated it for another CPU family. I've been keeping an eye on AMD's job listings for a long time now to see how long positions remain open and for what, and comparing it to historical data that's available. They've been very busy hiring engineers the last year to year and a half. And that's just the US, for example.
I know as much as AMD's plans as you do, but in regard to your dig at Intel there... I think they're observing and learning from others' failures. If AMD can launch RDNA2 and Zen 3 with minimal bugs and squash them fast, then I'll be impressed.
Maybe more people will name their kids Zen and Ryzen. It's a trend apparently. Granted, you'd never name a child "Core" or worse, "10650U" unless they consumed a diet predominantly of lead paint chips from a bygone era and were a lost cause from the start.
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Smaller SIMD is faster and doesn't have a voltage-drive penalty to feed it. The design is still 4-issue Fixed point, 4-issue Floating point, 3-issue Address. The move from two 2x FMUL+2x FADD to one 4x FMA; means 128-bit workloads have 4x MUL or 4x ADD. There is also the benefit of only one FPPRF being present in the processor.
The core also needs to support X3D next year and logic-on-logic mock tests at TSMC went up to 3-Hi (Logic on logic on logic) in 2019. Having nuclear heat on a X3D stacked CPU for an absurd reason in supporting a 512-bit FMUL, 512-bit FADD, 512-bit FMUL, 512-bit FADD FPU would kill that project. Instead, it is better to revise and acknowledge a "no excuse" architecture that can push core count up with 3d-stacks and still push higher clocks.
Going forward...
5nm => higher fmax than 7nm
3nm => higher fmax than 5nm
2nm => higher fmax than 3nm
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coercitiv
Diamond Member
- Jan 24, 2014
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Looks like common sense is winning at AMD HQ and they'll go straigth to 5000 series to fix the mobile naming blunder:
https://videocardz.com/newz/amd-ryzen-9-5900x-to-feature-12-cores-ryzen-7-5800x-gets-8
https://videocardz.com/newz/amd-ryzen-9-5900x-to-feature-12-cores-ryzen-7-5800x-gets-8
"new IO chip with better memory controller" <== in reference to this...
IOD for Milan is the same as Rome. While, the IOD for Vermeer is still Bixby.
Only Stones, Badami, and Raphael uses Durango.
City: Promontory || (Just a chipset)
City: Bixby || (Both IOD&Chipset) <== 14nm/12nm IOD
City: Durango || (IOD & Chipset again) <== 6nm IOD
Durango is the X3D IOD => Which interconnects to the X3D CCD & GCD/MCD through the same 2.5D interconnect.
Where TSMC's SOIC is today => AM6 w/ Durango IOD can have up to 12-Hi CCD/MCD(4-Hi CCD+8-Hi MCD) + 12-Hi GCD/MCD(4-Hi GCD+8-Hi MCD) or a second CCD stack. In top-end solutions, etc. Look at where the IO interface is in Matisse CCD and where the 8-ch TSV area is at on any HBM die, if you are wondering.
IOD for Milan is the same as Rome. While, the IOD for Vermeer is still Bixby.
Only Stones, Badami, and Raphael uses Durango.
City: Promontory || (Just a chipset)
City: Bixby || (Both IOD&Chipset) <== 14nm/12nm IOD
City: Durango || (IOD & Chipset again) <== 6nm IOD
Durango is the X3D IOD => Which interconnects to the X3D CCD & GCD/MCD through the same 2.5D interconnect.
Where TSMC's SOIC is today => AM6 w/ Durango IOD can have up to 12-Hi CCD/MCD(4-Hi CCD+8-Hi MCD) + 12-Hi GCD/MCD(4-Hi GCD+8-Hi MCD) or a second CCD stack. In top-end solutions, etc. Look at where the IO interface is in Matisse CCD and where the 8-ch TSV area is at on any HBM die, if you are wondering.
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That was reported over the summer or back in May or June around the time of the XT rumors. It makes a lot of sense. But will AMD do it? That's the million dollar question. Intel skipped the 1000 series, NVidia skipped a few generations, too. It's Videocardz, treat it as a rumor.
Gideon
Golden Member
- Nov 27, 2007
- 1,619
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Yeah, that naming really needs cleaning up.
I could understand naming the first APUs 2xxx series as it had fixed latencies and working boost, which made it very similar to desktop 2xxx series, only difference being 14nm vs 12nm.
But Picasso should never have been made the 3xxx series considering how vastly different it is from zen2 and how little it actually changed. I get it that OEMs request rebrands but IMO 2550U and 2750U should have sufficed.
Even when they did call it 3xxx they should have called Zen 2 desktop the 4xxx series.
Anyway, it's good to see them fixing this before AM5.
And well, compared to what Intel has AMD already does a brilliant job. Intel did a total brand redesign, logo and all, but somehow thought that keeping series "11" with 5-digit numbers was a great idea."i7 1185G7" just rolls of the tounge doesn't it?
They need a similar reset of numbering they did with Nehalem.
DrMrLordX
Lifer
- Apr 27, 2000
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I . . . don't specifically remember it being delayed, but it could just be my memory failing me.
moinmoin
Diamond Member
- Jun 1, 2017
- 4,944
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Nice, common sense won at videocardz and they are prominently tagging rumors as such.
As for the 5000 series rumor, let's hope so.
You may need to look into that. Put this on a thumbdrive and figure out how to boot from it.
May need to find out where your USB ports are. Vaseline may come in handy.
I'll see myself out.
DrMrLordX
Lifer
- Apr 27, 2000
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More importantly, they have drastically improved boost clocks if videocardz is accurate (and as of late, pretty much all the stuff WhyCry publishes has been dead on).
The 5900X also apparently boosts to 4.9 ghz, which leaves me wondering where the 5950X will boost to.
Around 6-6.2GHz or so on LN2 /s
We'll have to wait and see. With the per core clock and voltage control it seems like the magical 5GHz barrier could be a possibility.
Ajay
Lifer
- Jan 8, 2001
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I'd be more interesting in all-core clocks. Boosts seem to be very short lived, even playing a game.
If you are expecting all core 4.9 you will be disappointed. Short of a node shrink I don’t expect worst case suicide workloads to improve much at all unless AMD has made the Zen core itself more power efficient.
Where we likely WILL see improvement is in light/medium workloads. AMD could also possibly allow each core to consume more power, which means that cores will boost higher for nT workloads (but all core workloads would still throttle down).
All core workloads are limited first by TDP and second by power consumption limits. You can enable PBO to eliminate the TDP variable, but the power consumption limit couldn’t be worked around. That is why people think PBO is bugged IMO.
With Zen 3 the per core clock/voltages will allow a person to fine tune their cpu for certain use cases if wanted. I'd imagine even the power limit can be somewhat avoided as long as one chooses wisely. Of course we'd have to do a wait and see how it pans out in the end.
Isn't that exactly what AMD has stated as the main purpose of the Zen3 design, higher efficiency? All of the design changes are to this end, which can be used to have higher performance for same power, or the opposite, same performance for lower power, will be very useful for mobile.
DrMrLordX
Lifer
- Apr 27, 2000
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N7+ offers +10% performance at isopower vs N7 according to TSMC's own data. I doubt we'll see +10% max boost clocks, but we'll see that in the all-core boost. 4.4-4.6 GHz all-core boost is not out-of-the-question in "real world" AVX2 workloads (Blender, etc) depending on the SKU.
For example, most of the 3900X and 3900XT samples I've seen reviewed can vary in MT clocks during CBR20 between 4000 and 4200 MHz. Vermeer 12c should hit around 4.4 GHz in the same workload assuming they haven't done anything to make it more prone to hotspotting. Alternative, AMD could have just opted for lower power and tried to hold the same clocks.
Ajay
Lifer
- Jan 8, 2001
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I wasn't expecting that. Zen2 is limited by a couple of max current settings, package power and temperature.
Maybe? I assumed by efficient they meant parsing and routing incoming data better. Zen is already power efficient IMO compared to Intel. I dunno how much more AMD can drop power usage through various processor states and clock frequencies.
Thunder 57
Platinum Member
- Aug 19, 2007
- 2,674
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My rebuttal:
Apple Books TSMC's Entire 5nm Production Capability
Apple alone will soak up TSMC's 5nm capacity for the iPhone 12, iPad Air, and A14, leaving no room for anyone else.
Apple was 45,000 wafers for Q1/Q2/Q3... Q4 however is 20,000 wafers. (15,000 commited wafers to 6000 committed wafers); A14, A14X, Apple GPU.
AMD was 60,000 wafers for Q1/Q2/Q3... Q4 however is 90,000 wafers. (20,000 committed wafers to 30,000 committed wafers); Genesis(2.5D), Stones(3D), Arcturus(MI100), etc.
Common order capacity for Milan and other DDR4-3200 SoC that will not be named => 40,960 CCDs per customer quantity // ~60 day lead time to 2.5D/3D packaging facility and ~60 days lead time to SoC package in Singapore. Then, 60 days to HPE, Dell, etc.
Total capacity with Phase 1+Phase 2 for Q4 => 240,000 wafers per quarter. 240,000 - (90,000+20,000) => 130,000 wafers left over of overcapacity.
AMD+Apple = ~50% of wafers, rest is Hisilicon, Mediatek, and a few others.
We also know ARM was creating 5nm as well. Zeus N2 is both 7nm/5nm.
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