I would hazard a guess that the APUs will stay monolithic for at least the next two generations. My guess would be thatthe next APU generation uses the same 7nm tech that they are using now, but matured for yield purposes, and goes with a physically larger die (than the cpu chiplet from Matisse). I suspect that it will need to be around 50%-75% larger, will include a pair of 4 core CCX units with half the L3 as the current matisse chiplet, will have 12-14 Navi based CUs, and will have some of the improved IO characteristics of Matisse (more high speed USB3, etc.). I suspect that graphics performance will not be much more than 25-35% better than the 3XXX series APUs, but that is still more than enough for leadership in the market.
I don't see AMD doing anything amazing in the APU space until 7nm+/6-5nm is matured. By that point, the difference between the size of the package required to include all the needed pins for I/O and a monolithic die will be so drastic, that the package size will be simply massive as compared to the actual chip. With that much room, it will make sense, even in the mobile space, to go multi-chiplet in the APU, and that's where we may see AMD use a package with a CPU chiplet, an IO chiplet that includes an iGPU, and an HBM# chiplet. While 3D stacking is nice and all, in the mobile space, Z height is important too, and being able to spread the thermal load over a larger surface area will make for a less complex cooling setup. While I like Intel's idea, I have to think that it will be very thermally limiting.