Speculation: Ryzen 3000 series

[Abwx]

So interestingly the more expensive ROG line boards have worse support and that B450 boards have better support than X470.

The PCIe 4.0 situation is something I don't like about this launch and something holding me back from buying. I want PCIe 4.0 on the x16 and 1 m.2 but I don't want to pay the X570 price premium, power premium, or deal with the fan. Unfortunately this means waiting for B550 which means depending on other development may mean not buying in at all.

Low cost PCIe4 chipsets are to be released in Q4/19-Q1/20, that being said, and as pointed by Techreport, the X570will still be way better I/O wise.

 

[amd6502]

The core area is actually very small:

TSMC 7nm Ryzen 3 core (without L2): ~2.87 mm2
Intel 10nm Sunny Cove core (without L2): ~4.42 mm2

That is amazingly small. So ballpark 30mm2 for the 8 cores + L2 and somewhat above that for the L3 and just a tiny uncore.

All the parts so far have full L3, so I think any L3 defects will get binned to quadcore. There is going to be a 4c/8t Ryzen 5 (3500x?) arriving before Christmas I'm almost sure.

There is a small chance they would reserve some L3 defects to reuse in consoles. But I think most likely consoles get their own custom CCD with minimal L3 (25%/8MB?) Either that or they are produced as two chip MCM's (with GPU and CPU on same chiplet) that mirror and complement another.

A reply from someone high enough with AMD puts to rest any and all doubt.

8c/16t is a high volume seller, so a 3x MCM would be the worst way to do it, and secondly there is high demand for a lower end 7nm quad-core ryzen 5; therefore, squandering relatively rare quad-core salvage would make no sense. I also think I remember Lisa Su holding up the single chiplet package during CES when introducting the 3700x 3800x, and only when introducing the 12c part, holding up the "surprise-surprise" dual CCD 12-core flagship.


It does surprise me a little that one can pump just about 90+ watts through a single 70mm2 chiplet, where most that power goes to cores totalling under 30mm2 of area. https://www.anandtech.com/show/14605/the-and-ryzen-3700x-3900x-review-raising-the-bar/19

Sounds like the rumors are suggesting the MCM APUs might have been cancelled this round (I think Anandtech mentioned that in the interview with Lisa Su, and she said they hadn't said what that product would be but that its not cancelled - which I have a hunch just means there'll be monolithic Zen 2 APUs), and I'd guess that's due to the packaging issues of AM4.

[...]

Also with regards to that general talk, the rumors I saw said pretty much the opposite, that the dGPU Navi we're getting this year is a stopgap between GCN and the full architecture changes that is the basis for Navi, and that the next gen consoles will have the "real Navi" (and I'm guessing Arcteryx will bring most of that to the PC GPUs).

FP5 needs to be even smaller than AM4 I think? With the main strength of 7nm being power efficiency, I think a mobile oriented monolithic APU is just about certain. Again, whatever the Navi equivalent of Vega 8-10CU would be optimal. If they can get the whole APU in ~70mm2 and make it die salvagable as iGPU for the desktop oriented part that would be great.

 

[DarthKyrie]

But on AM4 they'd have problems packaging that. They might be able to fit a small GPU with a single stack of HBM in the spot of one of the CPU chiplets (but that GPU would be so small that I don't think it'd be worth it, and the costs for doing that wouldn't be), and I'm not sure they can move the I/O module's placement to put HBM by it. There's just not much room without changing the whole packaging and I'm not sure they're ready for that yet. So it might not be feasible until they can stack onto the HBM.

I think they both already said they're using GDDR6 on the next consoles so that's not gonna happen. The memory controller would either be in the I/O or on the GPU chiplets, as they'd have to have a special version of the CPU chiplet made since it has no memory controller at all (and definitely not a GDDR6 one).

Sounds like the rumors are suggesting the MCM APUs might have been cancelled this round (I think Anandtech mentioned that in the interview with Lisa Su, and she said they hadn't said what that product would be but that its not cancelled - which I have a hunch just means there'll be monolithic Zen 2 APUs), and I'd guess that's due to the packaging issues of AM4.



They say that its custom but I personally am skeptical that it will be drastically so. I'm very doubtful the CPUs will be, but the GPUs might.

Oh and I really don't think it would be for backwards compatibility since that shouldn't be that difficult since its x86 CPU and the GPU still adheres to general API. It'll need tweaking to run on the new hardware for sure though (Microsoft even said they have frozen adding games to backwards compatibility so they can focus on having what they've currently got working on the next system).

Also with regards to that general talk, the rumors I saw said pretty much the opposite, that the dGPU Navi we're getting this year is a stopgap between GCN and the full architecture changes that is the basis for Navi, and that the next gen consoles will have the "real Navi" (and I'm guessing Arcteryx will bring most of that to the PC GPUs).

The reason that the backward compatibility has been stuck in my head was that I remember watching something that had Phil and Lisa on stage and they were talking about some of the changes that went into Project Scarlett. I remember them talking about how there are changes in both the CPU and GPU to better support XBox 360 and the OG XBox games. There was another one with Lisa and Mark over at Sony talking about the changes made to both in order for the PS5 to support PS3 games natively. We will see soon enough if this really happens or not.

I remember it being discussed that NAVI 10 is basically called RDNA .5 and what will come in the XBox, PS5, and in the coming NAVI cards will be RDNA 1 which includes RT hardware.

 

[darkswordsman17]

The reason that the backward compatibility has been stuck in my head was that I remember watching something that had Phil and Lisa on stage and they were talking about some of the changes that went into Project Scarlett. I remember them talking about how there are changes in both the CPU and GPU to better support XBox 360 and the OG XBox games. There was another one with Lisa and Mark over at Sony talking about the changes made to both in order for the PS5 to support PS3 games natively. We will see soon enough if this really happens or not.

I remember it being discussed that NAVI 10 is basically called RDNA .5 and what will come in the XBox, PS5, and in the coming NAVI cards will be RDNA 1 which includes RT hardware.

Hmm, I'm trying to think what they meant by that. Short of them putting full on older system hardware in it, I don't know hardware changes they could make that would help that (I assumed it was talking about the One, and they'd just translate/emulate the older stuff since they'll have even more power to do that than before). Only thing I can think is them putting in extra large cache to function like the eDRAM buffer that the 360 and One originally had. Which I could see that being possible and AMD calls their large cache "GameCache" so that might hint. But that's in consumer Ryzen (but perhaps it was a change made to mostly appease the console makers, its just turned out to benefit consumers as well since now they just make all Zen 2 have large cache and reap economies of scale).

Which, maybe its just them talking about their decision to go with stronger CPU in order to enable better emulation? They could've probably easily settled for earlier Zen and/or fewer cores (with multi-threading) or no multi-threading and got a big boost over the Jaguar cores in the PS4/One. Perhaps also it was the motivator behind them deciding to go for high speed SSD to reduce overall system latency so it could run a virtual machine emulator environment while not having to force the whole system into some other software state so that they could have the main OS running and you could jump back to it immediately; which Microsoft was kinda already doing something like that on the One and I think that was part of the idea although some was also that I think they've been laying the groundwork for Xbox as a service where they'll do the same thin on PCs - run the Xbox OS as a virtual machine on Windows 10 enabling easy compatibility where it can auto adjust settings based on your hardware).

So, to me I figure they're more explaining the rationale of why they felt they should push for much stronger CPU and fast SSD to enable them to probably be able to maximize overall system latency so as to be able to overcome potential bottlenecks in emulation/translation performance. But adding hardware to the GPU to improve support of what will be 20 year old API would be very baffling to me. And I really don't know what they could to alter the CPU to better support games made for Cell or even Xenon

Yeah quite a bit of rumors were talking about "true Navi" being for the PS4. Will be interesting to see what it turns out as.

 

[rbk123]

Just checked my microcenter for stock and it looks like they've got 10+ 3700x's in stock, 2 3600x's and rest was wiped out. When I was there on Tuesday they had a boatload of 3600(x)'s in the case.

Also interesting is that they increased the closeout pricing of the 2700X from $199 to $219.

 

[AAbattery]

Here you are:

https://www.reddit.com/r/Amd/comments/can8yr/_/et9va3r

Not ... common enough ...

A reply from someone high enough with AMD puts to rest any and all doubt. I don't use Reddit and i'm having trouble locating the post in question so a little assistance in that regard would be much appreciated.

 

[HurleyBird]

New (much better quality) die shots from the same source as yesterday.

AMD@7nm(12nmIO)@Zen2@Matisse@Ryzen_5_3600@100-000000031_BF_1923SUT_9HM6935R90062___DSCx5@CCD_Infrared by https://www.flickr.com/photos/130561288@N04/https://www.flickr.com/photos/130561288@N04/

 

[extide]

Ohhh yeah thats nice.. Wow

EDIT: Ok, so there is a nice big one of the IO die as well. Some really interesting stuff visible now...



So, all of the interfaces are much more visible now. We can see all the same stuff as before. Note this is rotated 90 degrees to the left (CCW).

• So we have the DRAM PHY on the left -- you can see that it supports ECC. In each of the two sections you can see four large squares on the top -- and then 5 identical sections on the bottom part, each of these is 8-bits wide which makes 72-bits. Nice of AMD to put ECC here as this die may not get used on server parts at all.
• Then on the top we have the Infinity Fabric PHY. Here you can see a clear difference between the left and right half of each link. Now I am kind of curious if we are seeing a difference between the XMIT and RECV parts here. Each CCX has half as much write b/w as read b/w -- so the XMIT parts (from this end) should be larger -- but the left and right halves appear to be about the same size. Maybe the left half of each of these two areas is the XMIT (which would be the bigger link) and the right half RECV, and then the top and bottom halves would go to each CCX in each CCD. (Or maybe the left/right halves go to each CCX in each CCD, and then the top/bottom is XMIT/RECV?)
• There appears to be another smaller PHY in between the 2 IF links, and several smaller ones to the top right corner of the die. I wonder what these could be.
• Then on the bottom right and bottom let we can see two groups of 6 sections -- I am guessing that's the PHY for USB3.2 G1, a total of 12 ports.
• The large section on the bottom I believe is PCIe -- probably 32 lanes here. Zeppelin also had 32 lanes on each die, but still only exposed 24 in consumer SKU's. This allows the OEM's to do some customizing and perhaps using some of those same SERDES channels for other stuff like SATA.
• Then we have the two smaller blocks -- one of them on the bottom left just above the 6 USB 3.2 G1, and the other one on the bottom right but above the other 6 USB 3.2 G1. I was thinking these were SATA ports before but now that I think about it, I think these are USB 3.2 G2, 4 total ports.
• So, a couple more interesting parts. Right smack in the center of the die there is an area that has some pretty strong symmetry, almost looks like a pair of cpu cores but that doesn't really make sense. There is probably the PSP on here, but this area is much too large, an I think the PSP is just one core isn't it? More on the PSP below...
• Another interesting area is the 5 white sections towards the top middle -- four in a row and then one down -- kinda like the tetris piece. Right under that is a small square area with a lot of varied sections in it. I think the PSP is either this area or the area kinda up and to the left of the 'tetris piece' -- just below the left side of the left IF PHY.
• There is quite a bit of other logic in there -- no doubt much of it is the control logic for these many interfaces. Very cool photos. That whole top right corner is definitely mysterious, though...

Can you tell I love die shots?

 

[H T C]

Here you are:

https://www.reddit.com/r/Amd/comments/can8yr/_/et9va3r

Done.

 

[itsmydamnation]

Given like 50% is just L2+L3 cache , those chips must yield so well*.

So its basically like yielding a 40mm sq chip!




* its really easy to build cache line based physical redundancy

 

[LightningZ71]

Ohhh yeah thats nice.. Wow

EDIT: Ok, so there is a nice big one of the IO die as well. Some really interesting stuff visible now...



So, all of the interfaces are much more visible now. We can see all the same stuff as before. Note this is rotated 90 degrees to the left (CCW).

• So we have the DRAM PHY on the left -- you can see that it supports ECC. In each of the two sections you can see four large squares on the top -- and then 5 identical sections on the bottom part, each of these is 8-bits wide which makes 72-bits. Nice of AMD to put ECC here as this die may not get used on server parts at all.
• Then on the top we have the Infinity Fabric PHY. Here you can see a clear difference between the left and right half of each link. Now I am kind of curious if we are seeing a difference between the XMIT and RECV parts here. Each CCX has half as much write b/w as read b/w -- so the XMIT parts (from this end) should be larger -- but the left and right halves appear to be about the same size. Maybe the left half of each of these two areas is the XMIT (which would be the bigger link) and the right half RECV, and then the top and bottom halves would go to each CCX in each CCD. (Or maybe the left/right halves go to each CCX in each CCD, and then the top/bottom is XMIT/RECV?)
• There appears to be another smaller PHY in between the 2 IF links, and several smaller ones to the top right corner of the die. I wonder what these could be.
• Then on the bottom right and bottom let we can see two groups of 6 sections -- I am guessing that's the PHY for USB3.2 G1, a total of 12 ports.
• The large section on the bottom I believe is PCIe -- probably 32 lanes here. Zeppelin also had 32 lanes on each die, but still only exposed 24 in consumer SKU's. This allows the OEM's to do some customizing and perhaps using some of those same SERDES channels for other stuff like SATA.
• Then we have the two smaller blocks -- one of them on the bottom left just above the 6 USB 3.2 G1, and the other one on the bottom right but above the other 6 USB 3.2 G1. I was thinking these were SATA ports before but now that I think about it, I think these are USB 3.2 G2, 4 total ports.
• So, a couple more interesting parts. Right smack in the center of the die there is an area that has some pretty strong symmetry, almost looks like a pair of cpu cores but that doesn't really make sense. There is probably the PSP on here, but this area is much too large, an I think the PSP is just one core isn't it? More on the PSP below...
• Another interesting area is the 5 white sections towards the top middle -- four in a row and then one down -- kinda like the tetris piece. Right under that is a small square area with a lot of varied sections in it. I think the PSP is either this area or the area kinda up and to the left of the 'tetris piece' -- just below the left side of the left IF PHY.
• There is quite a bit of other logic in there -- no doubt much of it is the control logic for these many interfaces. Very cool photos. That whole top right corner is definitely mysterious, though...

Can you tell I love die shots?

For the IO die shot, and identifying the various other sections, remember that this package will likely also be used for Ryzen AND EPYC embedded projects. There are surely multiple Ethernet interfaces there. There's likely Enterprise level interface and control IO links in there as well. I believe that Serve the Home reviewed a couple of the embedded EPYC products based on Summit and Pinnacle ridge, so you can likely get an almost full list of all of the blocks that get exposes there. In addition, remember that this floorplan was reused for X570, so everything in the chipset is in there as well.

 

[extide]

For the IO die shot, and identifying the various other sections, remember that this package will likely also be used for Ryzen AND EPYC embedded projects. There are surely multiple Ethernet interfaces there. There's likely Enterprise level interface and control IO links in there as well. I believe that Serve the Home reviewed a couple of the embedded EPYC products based on Summit and Pinnacle ridge, so you can likely get an almost full list of all of the blocks that get exposes there. In addition, remember that this floorplan was reused for X570, so everything in the chipset is in there as well.

Yeah, I bet a couple of the interfaces on the top right are Ethernet, yeah forgot about that last night.

 

[amd6502]

And the cache coherency to keep the two L3's on the two separate 7nm chiplets must take up a good amount of area? It may one/some of the bulky blocks in the center.

 

[itsmydamnation]

And the cache coherency to keep the two L3's on the two separate 7nm chiplets must take up a good amount of area? It may one/some of the bulky blocks in the center.

No different then on zeppelin really. Those big sram arrays near the DDR interface were there in zepplin as well, they are probably the location of a directory or some other type of tracking mechanism . Infact with the BIg I/O coherency becomes significantly easier for Rome compared to Naples.

 

[jpiniero]

Die shot makes me think the APU is going to be 8 core and they will cut the L3 in half or more.

 

[LightningZ71]

I would hazard a guess that the APUs will stay monolithic for at least the next two generations. My guess would be thatthe next APU generation uses the same 7nm tech that they are using now, but matured for yield purposes, and goes with a physically larger die (than the cpu chiplet from Matisse). I suspect that it will need to be around 50%-75% larger, will include a pair of 4 core CCX units with half the L3 as the current matisse chiplet, will have 12-14 Navi based CUs, and will have some of the improved IO characteristics of Matisse (more high speed USB3, etc.). I suspect that graphics performance will not be much more than 25-35% better than the 3XXX series APUs, but that is still more than enough for leadership in the market.

I don't see AMD doing anything amazing in the APU space until 7nm+/6-5nm is matured. By that point, the difference between the size of the package required to include all the needed pins for I/O and a monolithic die will be so drastic, that the package size will be simply massive as compared to the actual chip. With that much room, it will make sense, even in the mobile space, to go multi-chiplet in the APU, and that's where we may see AMD use a package with a CPU chiplet, an IO chiplet that includes an iGPU, and an HBM# chiplet. While 3D stacking is nice and all, in the mobile space, Z height is important too, and being able to spread the thermal load over a larger surface area will make for a less complex cooling setup. While I like Intel's idea, I have to think that it will be very thermally limiting.

 

[jpiniero]

Still think GDDR6 is the way to go. Obviously that would limit the usage to mobile but I think it would be pretty easy to implement.

 

[amd6502]

Because 4c/8t would have a very big power savings advantage over 8c/16t I think the monolithic APU would be quadcore. Whether it's Zen2 or Zen3 is harder to guess imho.

There's no reason (afaik) that they cannot put out an APU using the current Zen2 CCD chiplet so that they can address the upper niche markets, as well as launch significantly earlier than the arrival date of the mobile focused APU. All it would take would be a modified IOX with Vega graphics (with 6 to 8CU or so); or perhaps even the current IOX along with a GPU chiplet designed to fit the current package. That's enough to address the OEM and DIY 720p gaming market in devices such as all in ones, sff desktops, and gaming plus elite-compute 17" laptops.

 

[BigDaveX]

There's no reason (afaik) that they cannot put out an APU using the current Zen2 CCD chiplet so that they can address the upper niche markets, as well as launch significantly earlier than the arrival date of the mobile focused APU. All it would take would be a modified IOX with Vega graphics (with 6 to 8CU or so); or perhaps even the current IOX along with a GPU chiplet designed to fit the current package. That's enough to address the OEM and DIY 720p gaming market in devices such as all in ones, sff desktops, and gaming plus elite-compute 17" laptops.

They're going to need to start pushing out more APUs sooner or later. Honestly, their current APU range feels like something of an afterthought compared to the full-fledged CPUs - which, weirdly enough, is the complete opposite of the situation they had in the post-Bulldozer-pre-Zen era - and they're not going to make any serious traction against Intel in the OEM market (and by extension, the CPU market in general) unless they start putting out more processors that don't need discrete GPUs.

 

[moinmoin]

They're going to need to start pushing out more APUs sooner or later. Honestly, their current APU range feels like something of an afterthought compared to the full-fledged CPUs - which, weirdly enough, is the complete opposite of the situation they had in the post-Bulldozer-pre-Zen era - and they're not going to make any serious traction against Intel in the OEM market (and by extension, the CPU market in general) unless they start putting out more processors that don't need discrete GPUs.

The current APU range *is* an afterthought, both time wise and financially. AMD releases APUs last as they prefer to settle their CPU gen and use of process node first, then adapt it to a monolithic die. And the current APUs have really lackluster margins, they are the lowest cost Zen based chips consumers can buy even though they use the biggest Zen based dies that aren't even usable in AMD's highest margin market, data centers. That's a miserable TAM.

I expect AMD to push APUs more whenever they are no longer monolithic. Once their APUs are MCM packages with small dies AMD finally can increase the margin per die, with the added bonus of having the flexibility of being able to offer optimized small (Athlon) to big (comparable to consoles/Subor Z+) APUs. But as these have no market in data centers such a product range clearly isn't a pressing issue to AMD (yet?).

 

[maddie]

The current APU range *is* an afterthought, both time wise and financially. AMD releases APUs last as they prefer to settle their CPU gen and use of process node first, then adapt it to a monolithic die. And the current APUs have really lackluster margins, they are the lowest cost Zen based chips consumers can buy even though they use the biggest Zen based dies that aren't even usable in AMD's highest margin market, data centers. That's a miserable TAM.

I expect AMD to push APUs more whenever they are no longer monolithic. Once their APUs are MCM packages with small dies AMD finally can increase the margin per die, with the added bonus of having the flexibility of being able to offer optimized small (Athlon) to big (comparable to consoles/Subor Z+) APUs. But as these have no market in data centers such a product range clearly isn't a pressing issue to AMD (yet?).

Is it possible that when the Zen project started, they saw mobile/lower end markets facing increasing competition from ARM? Remember they had an ARM core in early development simultaneously. With little capital, the smarter move seemed to be going for the server market using multi-chip designs to lower costs below the competition with the spillover being very competitive for the desktop as well, especially in value/$. There is only one competitor in these markets versus many financially healthy ones in ARM.

 

[moinmoin]

Is it possible that when the Zen project started, they saw mobile/lower end markets facing increasing competition from ARM? Remember they had an ARM core in early development simultaneously. With little capital, the smarter move seemed to be going for the server market using multi-chip designs to lower costs below the competition with the spillover being very competitive for the desktop as well, especially in value/$. There is only one competitor in these markets versus many financially healthy ones in ARM.

I don't think AMD was worrying about ARM, in low end markets or elsewhere. AMD's Zen based products so far has been about reaching the biggest possible TAM with the fewest possible distinct die designs. Data centers is the one single highest margin market for x86 chips. So for Zen scalability to as many cores as possible became AMD's primary focus. But APUs don't require upward scalability, and the restriction on distinct die designs made more than one optimized APU die unfeasible. This is where we still are today, and the only way I see AMD doing more with APUs (trying to increase its ever so limited TAM) is by stopping creating them as monolith dies.

 

[jpiniero]

Getting the corporate market to use AMD is not going to be easy. And consumers, outside of gamers and Apple, is pretty much buying Chromebooks these days (and the Windows equivalent ie: no margin). Much easier to get the Cloud Guys to buy Epyc.

 

[LightningZ71]

I see AMD's APU efforts as just being completely optimized for low cost. They release them on a node that is already settled in as high yield with low risk. They target them where they make the most sense, the embedded market, the lower end mobile market, and the AOI/Low cost business market. All of those still push healthy volume and have room for AMD to make volume in without having to have a leading edge product. As it is, AMD needs GloFo volume to meet their wafer agreements, and what better way to do that than with their APUs? I honestly wouldn't be completely shocked if the next APU is STILL based on 12nm GloFo, but includes NAVI CUs and a core that is more like Zen2 with an updated memory controller. Its not like their wafer agreement is completely gone yet. The IO wafers are only going to cover so much of that. Also, remember, they are also producing a tiny 12nm die with just two cores and a tiny iGPUs as well for the embedded and lowest end mobile market. Save for power, it is still one of the fastest chips in its end of the market.

 

[amd6502]

I see AMD's APU efforts as just being completely optimized for low cost. They release them on a node that is already settled in as high yield with low risk. They target them where they make the most sense, the embedded market, the lower end mobile market, and the AOI/Low cost business market
[....]
Also, remember, they are also producing a tiny 12nm die with just two cores and a tiny iGPUs as well for the embedded and lowest end mobile market. Save for power, it is still one of the fastest chips in its end of the market.

Traditionally yes, and I think they will continue this with Picasso APU which should remain in the market a few years and its half sized "Raven2" or whatever it's called. However now they have the opportunity to go for ULP high end focused 7nm APU which should have better margins and still be high volume.

They should be able to do something like a 7.5W part that performs (cpu-wise) better than Picasso at 15W. And aim for a sub 100mm2 die size.

As far as WSA, I don't know what was negotiated. GF did cancel their finfet node shrink, so it should relieve AMD of obligations to some extent.

In any case, you have Picasso, Raven2, server IOX, consumer IOX, P11, and the Polaris 12nm refresh definitely contributing to the WSA already. I think there's a good chance Pinnacles will continue to be produced another year or longer; I think it could be the new long-lived value workhorse like Vishera. (Current gen consoles, do they go towards the WSA? They may remain in production a while.) Then, assuming an MCM APU to target OEM/sff desktop, either a Vega chiplet (~60mm2) or Vega IOX (~150mm2) would also be 12/14nm GF made. And lastly there is some chance of a GF produced FDX APU for the ulta low end.