Speculation: Ryzen 3000 series

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What will Ryzen 3000 for AM4 look like?


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Dec 6, 2018
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These die pictures are really nice high resolution, better than what we had on Zen(+)
is this official released?
 
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Tuna-Fish

Senior member
Mar 4, 2011
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These die pictures are really nice high resolution, better than what we had on Zen(+)
is this official released?
No. This is the result of an enthusiast figuring out that silicon is transparent to near IR, and getting/making the necessary equipment to take a photograph directly through the silicon. And then, through trial and error, got really good at it.

His flickr: https://www.flickr.com/photos/130561288@N04/

(you can tell these are all his shots because he chipped the cpu chiplet while delidding)

NOT L1$!
FPU 2x256bit
Yeah. Thing in the very back of the core is the FPU. L1i is at the far other end.
 

amd6502

Senior member
Apr 21, 2017
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EDIT: Here is my take on an annotation:
Looking at the free CCD slot, does it look like to any of you that the data from the fabric runs to points beneath the L3?

I agree with
To nie jest L1$!

FPU 2x256bit

NOT L1$!
FPU 2x256bit
because it makes sense that the doubled up FPU is going to take lots of transistors, and also because the L1 seems to fit better near the L2. So taking HurleyBird's enhancment https://forums.anandtech.com/threads/speculation-ryzen-3000-series.2558009/post-39869231 together with AMDK11's tip, and making a guess about the L1, it might be something like:
Zen2guess-ccd-hurley.png
 
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Nov 18, 2009
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www.teraknor.net
Looking at the free CCD slot, does it look like to any of you that the data from the fabric runs to points beneath the L3?

I agree with


because it makes sense that the doubled up FPU is going to take lots of transistors, and also because the L1 seems to fit better near the L2. So taking HurleyBird's enhancment https://forums.anandtech.com/threads/speculation-ryzen-3000-series.2558009/post-39869231 together with AMDK11's tip, and making a guess about the L1, it might be something like:
View attachment 8486

Yeah I do believe it does connect to the middle between the L3 banks of each CCX -- right where you have placed the CCM labels.
Check out this pic of the substrate -- you can see all of the links.



Looking at the new higher res photos, I do think that he is correct about the L1, and it is where you are placing the labels.
 

Antey

Junior Member
Jul 4, 2019
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hey guys, kind of new here.

i'm just wondering if quad channel would have any effect in gaming. i'ts clear that thredripper will demolish ryzen in productivity tasks (more cores) but what about gaming? does that amount of memory banwidth have any performance impact in gaming?

and what about cache? would 128-256 mb of cache affect gaming? or it is part of each ccx so it doesn't matter when all the cores or ccx are not being used?
 

Atari2600

Senior member
Nov 22, 2016
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Nope, no effect from extra memory channels. We've see than before with TR1 and TR2 vs Ryzen1 and 2.

Cache change might affect gaming, but you'll likely see more benefit from locating as many threads as possible under common L3 for lower latency - so you likely won't see an advantage from the extra L3 cache as they are on additional chiplets which are across the infinity fabric.
 

maddie

Platinum Member
Jul 18, 2010
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We're going to have 16C/memory channel if TR goes to 64C. Will be interesting, as there is already a small effect running 8C/channel on AM4.
 

amd6502

Senior member
Apr 21, 2017
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We're going to have 16C/memory channel if TR goes to 64C. Will be interesting, as there is already a small effect running 8C/channel on AM4.
TR had longer latencies, since the Zeppelin dies were a network connected to each other. Now that there is a central hub, latencies will be low. So the handicaps vs ryzen vanish and it should show its advantages more consistently.

I don't think TR 3000 will have a huge core count advantage over 16c, but the fact that the IO is faster on the TR motherbird will give 16c TR a significant advantage over 16c ryzen in heavy multithread, and perhaps even to a lesser but significant extent in gaming.

I believe TR 3000 will top out at 24c (3 x 8c chiplets), and also be available in 12c and 16c. Perhaps 8c with elite frequencies as well.
 

maddie

Platinum Member
Jul 18, 2010
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TR had longer latencies, since the Zeppelin dies were a network connected to each other. Now that there is a central hub, latencies will be low. So the handicaps vs ryzen vanish and it should show its advantages more consistently.

I don't think TR 3000 will have a huge core count advantage over 16c, but the fact that the IO is faster on the TR motherbird will give 16c TR a significant advantage over 16c ryzen in heavy multithread, and perhaps even to a lesser but significant extent in gaming.

I believe TR 3000 will top out at 24c (3 x 8c chiplets), and also be available in 12c and 16c. Perhaps 8c with elite frequencies as well.
Are you really predicting that TR3 will regress in core count versus TR2? In all seriousness, did you forget a [ /humor] at the end?
 

Markfw

CPU Moderator, VC&G Moderator, Elite Member
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May 16, 2002
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TR had longer latencies, since the Zeppelin dies were a network connected to each other. Now that there is a central hub, latencies will be low. So the handicaps vs ryzen vanish and it should show its advantages more consistently.

I don't think TR 3000 will have a huge core count advantage over 16c, but the fact that the IO is faster on the TR motherbird will give 16c TR a significant advantage over 16c ryzen in heavy multithread, and perhaps even to a lesser but significant extent in gaming.

I believe TR 3000 will top out at 24c (3 x 8c chiplets), and also be available in 12c and 16c. Perhaps 8c with elite frequencies as well.
So they are goiing down from 32 core to 24 core ? No way. I say at least 48 core, maybe the whole 64.
 

amd6502

Senior member
Apr 21, 2017
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So they are goiing down from 32 core to 24 core ? No way. I say at least 48 core, maybe the whole 64.
Half of the 32C's are compute threads. With the doubled up FPU, frequency+power efficiency, and IPC increase a 24c should more often than not match the multithread of the previous 32c threatripper. 24c zen2 is overkill for even the most serious of workstations.

Base clock will improve substantially from the 3ghz on 2990wx; suppose it's 3.6ghz, a 20% increase. Add 13% IPC increase, and you see it's equivalent to a 32 core of the prev gen. I'd say a 3.75+ghz base frequency and similar to slightly better boost than Ry 9 is pretty realistic.

Add into the account the better latencies, especially for the compute dies, and it surpasses the current flagship in pretty much all respects. IMHO it just makes sense to reserve 64 thread or higher Zen2 for the server line.

Secondly, the memory channels per core are more balanced than on TR 2990wx with a 24c product.

I would think a BGA socketed 32c Epyc (embedded) board solution would be just about as price competitive as a threatripper if it were on LGA. So it would make little sense anyways to go via threatripper if you want 64 threads.

Are you really predicting that TR3 will regress in core count versus TR2? In all seriousness, did you forget a [ /humor] at the end?
Yes, and no kidding. The thing is, because of perf/watt gains in 7nm and other reasons, it will be anything but a performance regression.
 
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Antey

Junior Member
Jul 4, 2019
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thank you! i read that Lisa Su said after computex (i think it was an answer to a question from the anandtech team) that if ryzen is moving up then threadripper will have to move up, up. that could mean moving to 48-64 core. or who knows...
 

Markfw

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Half of the 32C's are compute threads. With the doubled up FPU, frequency+power efficiency, and IPC increase a 24c should more often than not match the multithread of the previous 32c threatripper. 24c zen2 is overkill for even the most serious of workstations.

Base clock will improve substantially from the 3ghz on 2990wx; suppose it's 3.6ghz, a 20% increase. Add 13% IPC increase, and you see it's equivalent to a 32 core of the prev gen. I'd say a 3.75+ghz base frequency and similar to slightly better boost than Ry 9 is pretty realistic.

Add into the account the better latencies, especially for the compute dies, and it surpasses the current flagship in pretty much all respects. IMHO it just makes sense to reserve 64 thread or higher Zen2 for the server line.

Secondly, the memory channels per core are more balanced than on TR 2990wx with a 24c product.

I would think a BGA socketed 32c Epyc (embedded) board solution would be just about as price competitive as a threatripper if it were on LGA. So it would make little sense anyways to go via threatripper if you want 64 threads.



Yes, and no kidding. The thing is, because of perf/watt gains in 7nm and other reasons, it will be anything but a performance regression.
I don't doubt that memory on 24c will be better than on 2990wx, but Lisa Su said there would be more cores. And some people (like me) can use all the cores they can get, so for me, even 64 is not overkill. I have over 500 cores right now, and by putting more cores in one box, and having less boxes, I save electricity. That a big deal when you have a $600 a month electric bill. (the one I paid today was actually $606)
 

Thibsie

Junior Member
Apr 25, 2017
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Anyway, from a strict marketing point it would be suicide not to go to at least the same number of cores.
 

dlerious

Senior member
Mar 4, 2004
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TR had longer latencies, since the Zeppelin dies were a network connected to each other. Now that there is a central hub, latencies will be low. So the handicaps vs ryzen vanish and it should show its advantages more consistently.

I don't think TR 3000 will have a huge core count advantage over 16c, but the fact that the IO is faster on the TR motherbird will give 16c TR a significant advantage over 16c ryzen in heavy multithread, and perhaps even to a lesser but significant extent in gaming.

I believe TR 3000 will top out at 24c (3 x 8c chiplets), and also be available in 12c and 16c. Perhaps 8c with elite frequencies as well.
I don't see an 8 core considering they dropped it from their 2nd gen TR. 3rd gen 16 core would have to be renamed since they already have a 3950X. I wouldn't be surprised if they start at 24 and go to at least 48. Everything seems to be 6 or 8 core chiplets right now, so a 24-core could be 4x6. I'd be interested in how they'll be arranged - i.e..dummy dies?
 

dlerious

Senior member
Mar 4, 2004
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I would think a BGA socketed 32c Epyc (embedded) board solution would be just about as price competitive as a threatripper if it were on LGA. So it would make little sense anyways to go via threatripper if you want 64 threads.
When did AMD change the SP3 socket from LGA to BGA?
 

moinmoin

Senior member
Jun 1, 2017
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We're going to have 16C/memory channel if TR goes to 64C. Will be interesting, as there is already a small effect running 8C/channel on AM4.
Did you already get a 3950X? :p
That aside this may actually explain why memory write bandwidth is halved on Ryzen 3k, a balancing act to avoid the link being saturated too often?
 

amd6502

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Apr 21, 2017
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I have over 500 cores right now, and by putting more cores in one box, and having less boxes, I save electricity. That a big deal when you have a $600 a month electric bill. (the one I paid today was actually $606)
OMG I can't imagine! What are you doing with a supercomputer cluster?? Perhaps try to run closer to peak perf/watt (of the system) during the non-heating season; try ~2ghz-2.4ghz for the summer.

I don't see an 8 core considering they dropped it from their 2nd gen TR. 3rd gen 16 core would have to be renamed since they already have a 3950X. I wouldn't be surprised if they start at 24 and go to at least 48. Everything seems to be 6 or 8 core chiplets right now, so a 24-core could be 4x6. I'd be interested in how they'll be arranged - i.e..dummy dies?
Yes, probably no 8c. I think 12-24 sounds reasonable but who knows. 32c might be in the cards. For 24c, 3*8c seems more likely than 4*6c.

When did AMD change the SP3 socket from LGA to BGA?
I think it would be on similar or same as 3000 Epyc series, SP4, or SP4r2 or something; these are non-socketed BGA embedded. If you had a 32c/64t beast, the upgrade inability with BGA boards would be a non-issue; it's going to remain capable for well over a decade, as we're seeing the end of Moore's law and diminishing returns on tech; the platform features are going to outdate before the processor.

That aside this may actually explain why memory write bandwidth is halved on Ryzen 3k, a balancing act to avoid the link being saturated too often?
Do you mean the per core write bandwidth? It is 1/cycle in Zen2. Was it 2/cycle in Zen1?
 
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Abwx

Diamond Member
Apr 2, 2011
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Yes, probably no 8c. I think 12-24 sounds reasonable but who knows. 32c might be in the cards. For 24c, 3*8c seems more likely than 4*6c.
4 x 6 would provide more L3 than 3 x 8, that s a selling point for those highly priced CPUs, otherwise it would end with less L3/core than a (mainstream...) 3900X.

They will surely go up to 48C, at 64 it would be counterproductive as a 64C Epyc is priced about 8000$, they cant just sell those for 3000$, even with half the RAM bandwith.
 

moinmoin

Senior member
Jun 1, 2017
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Do you mean the per core write bandwidth? It is 1/cycle in Zen2. Was it 2/cycle in Zen1?
No, the IF bandwidth from CCD to IOD (but not the other direction) appears to be halved according to Aida64, meaning one needs two CCDs (so 3900X or 3950X) to make use of the whole memory write bandwidth. It already has been mentioned elsewhere on this board (though I can't find it anymore right now) and it's also confirmed as a design decision by AMD.

Random example graph after a quick google:
 

beginner99

Diamond Member
Jun 2, 2009
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3rd gen 16 core would have to be renamed since they already have a 3950X
I mean 3950x is at the top in terms of numbering for 3rd series. Would be awkward if all TRs models had to squeeze in there before 4000. So naming has to be changed for the whole TR lineup.

TR could start at 18 cores, 3x6, albeit I'm not sure how only 2 or 3 chiplets is possible. How is this done on Ryzen? Considering heatsink mount pressure. Sure not even with that empty space below IHS?
 

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