So, what are we guessing the R3XXX product stack will look like?
With the way that AMD has, in the past, configured their CPUs, they will likely have recovered chiplets in 6, 4 and 2 operational core versions. The question is, is there sufficient cost recovery in reusing the chiplets that have only 2 working cores? In anything other than the TR and EPYC, they are better served by using the Picasso chips at 4 cores to serve that market.
We have the 2 chiplet versions in 2 X 8 core, high clocked, and 2 X 8 core low clocked as well as 2 X 6 core high clock and 2 X 6 core low clock. Will we also see 2 X 4 core high clock and 2 X 4 core low clock as well as 2 X 2 core in high clock and low clock in OEM parts? Then, there are the single chip version in 1 X 8 core and 1 X 6 core?
Here's my guess:
For the R3800X, they will use 2 X 8 cores that clock well, likely only thermally and power limited. 64 MB L3
For the R3800, its 2 X 8 cores that don't clock as well, no PBO 64 MB L3
For the R3700X, they will use 2 X 6 core chiplets that clock extremely well. This will likely be the single thread champion in the 2 chiplet group. It'll also likely give some of the best memory throughput numbers per thread with having 64 MB of L3 feeding 24 threads.
For the R3700, they will use 2 X 6 core chiplets, lower clocks, no PBO 64 MB L3
For the R3600X, it'll be a single 8 core chiplet at full performance 32 MB L3
For the R3600, it'll be a single 8 core chiplet at reduced clock, no PBO 32MB L3
For the R3500X, it'll be a single 6 core chiplet at full performance 32 MB L3
For the R3500, it'll be a single 6 core chiplet at reduced performance. 32 MB L3
For the R3400, there will be the R3400G at 4 cores, 8 threads, APU 4 MB L3
For the R3300, there will be the R3300G at 4 cores, 8 threads, with a reduced clock and reduced GPU CU count 4 MB L3
For the R3200, there will be the R3200G with 4 cores, 4 threads, reduced GPU CU count 4 MB L3
Then there's the Athlon 300/320/340 at 2 cores, 4 threads, differing clocks. 4 MB L3
This also leaves room for a R3400X OEM chip that uses 2 X 2 core chiplets with PBO if yields on working cores for chiplets are bad. 32 MB L3
So, where do the 4 core and 2 core recovery chiplets go? Epyc and Threadripper. The only functional internal difference between them will be the number of working DRAM channels. TR3 will essentially be only EPYCs that have a failed DDR channel.
I'm thinking that there will be a TR3 lineup like so:
3920 - 8 X 2 core chiplet, 16 cores, likely half L3 cache at 128 MB
3950 - 8 X 4 core chiplet, 32 cores, 256 MB L3
3970 - 8 X 6 core chiplet, 48 cores 256 MB L3
3990 - 8 X 8 core chiplet, 64 cores 256 MB L3
All but the 3990 are using recovered chiplets. The 3990 will be a premium product and will command a high price because of it, justifying using the precious 8 core chiplets. The lower end TR3 line can certainly use the volume of 2 and 4 core chiplets if yields are reasonably good, and still get a premium from them. The EPYC can also do the same. As time moves on, and yields improve, if the mix of 8 core chiplets is just extreme, then AMD can shift production to using the fewest number of chiplets like so
3910 - 2 X 8 core chiplets, 16 cores full cache, 64 MB L3
3940 - 4 X 8 core chiplets, 32 cores full cache, 128 MB L3
3960 - 6 X 8 core chiplets, 48 cores full cache, 192MB L3
All this assumes that the information on the chiplets having 32MB of L3 is true. Halve the numbers if it isn't.
I know this is all speculation, but it looks like a solid product stack to me, and also an extremely competitive one with anything Intel will be offering.