Speculation: Ryzen 3000 series

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What will Ryzen 3000 for AM4 look like?


  • Total voters
    182

Mopetar

Diamond Member
Jan 31, 2011
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So, what are we guessing the R3XXX product stack will look like?
R9 - 16 cores (2x 8)
R7 - 12 cores (2x 6)
R5 - 8 cores (1x 8)
R3 - 6 cores (1x 6)
Athlon - 4 cores (1x 4)

I think that we'll probably only get ~3 different models in each of those ranges, mostly because AMD doesn't lock down their chips. We'll see a regular part that you can still OC, a top-end part that has higher guaranteed clocks, and likely a low power part that has slightly lower clocks, but falls into a lower TDP bucket. The low-TDP part will definitely exist for the R7 and R9. We might see some additional parts that occupy a particular niche like an R5 binned for absolute maximum clocks sold as an extreme gaming part.

For ThreadRipper, I don't think they release anything with fewer than 24 cores. There will probably be ThreadRipper parts that only contain 4 active chiplets, rather than using 8 chiplets that have a large amount of disabled cores.

I'm also rather skeptical about whether they'll release any parts containing chiplets with only active cores. Assuming that they do that at all, those would most likely wind up in a specialty server chip designed for high clock speeds, but low core count because there is a market niche for those there.
 

Mopetar

Diamond Member
Jan 31, 2011
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I've seen some fellow members point out "yields must be bad" if AMD needs to use lots of "defective" chiplets for their Zen 2 chips but that may not necessarily be the case:

View attachment 2875

For the purposes of the above pic's example, let's assume AMD will make 3 CPUs with 12 cores (two chiplets) @ 2.2 GHz, 2.6 GHz, and 3 GHz. It's quite possible to have a fully functioning 8 core chiplet to be used with 6 / 12 core CPU: all it needs is lower clock speed on some of the cores (than intended for the CPU), and those cores can be fused off.

What i'm trying to say is that it's possible for AMD to use fully functioning chiplets in lower segmentation (than 8 / 16 cores) without it being because of bad yields.
I think it depends on how AMD goes about testing and binning their chips. It's entirely possible that an 8-core chip that can only hit 3 GHz across all cores, could be used as a 6-core chip that can hit 4 GHz across all cores due to one or two of the cores being particularly bad.

If AMD can get more value from a 4 GHz 6-core chiplet than a 3 GHz 8-core chiplet, I think it's pretty obvious that they'll use it as a 6-core part, especially if the yields are good and there's no shortage of 8-core parts. I think that this is definitely the case in instances where there are one or two cores that are really holding the chiplet back.

Perhaps the level of testing will be increased simply because they have so many different product categories with different needs, which means spending additional resources on the binning process is likely to save them a lot of money in the long run by making sure that they utilize their chiplets as efficiently as possible.
 
Apr 27, 2000
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Athlon - 4 cores (1x 4)
Are you sure AMD will release a product like that based on Zen2? The only existing Athlons in AMD's post-Zen family are the 200/220/240GE which are based on Raven Ridge, not Summit Ridge or Pinnacle Ridge. If AMD is going to release another set of Athlon chips, I would expect them to be based on Picasso.
 

MaxDepth

Diamond Member
Jun 12, 2001
8,759
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I have no insider information plus my knowledge of the current architecture is sorely lacking but I do know crowd expectation.

People are willing to exchange energy consumption for good to middling gains. I know a GPU is completely different than a CPU but the last iterations of the Radeon have brought the same complaint. There is no headroom for overclocking because they've squeezed the chips for performance as much as they can and have brought in heat and power consumption that puts them more costly to run than others.

So here, while the Ryzen 5 2600x has been lauded as a good buy from a lot of PC enthusiasts and websites, people's attention is focused on power draw. So to me, if they can meet or beat the current Core i9-9900K with a much lower power consumption, then I can see a whole new breath of life for AMD. Yes, yes Threadripper is a marvel but that didn't equate yet to taking over sales in the small end server and high end desktops yet. It's a good position but not the champion in terms of sales.
 

Mopetar

Diamond Member
Jan 31, 2011
4,445
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Are you sure AMD will release a product like that based on Zen2? The only existing Athlons in AMD's post-Zen family are the 200/220/240GE which are based on Raven Ridge, not Summit Ridge or Pinnacle Ridge. If AMD is going to release another set of Athlon chips, I would expect them to be based on Picasso.
I don't have any insider knowledge or anything like that, but I suspect that eventually they'll have some 4-core parts that are sold as a really low-end part assuming that they can't find some other use for them. Even with 6-core being the new entry level chip, there will still be people who don't want that or would rather spend less money than AMD wants to charge for Ryzen.

There was some discussion earlier about whether or not they eventually move to a chiplet approach with their APU parts, so that's a possibility as well.
 

moinmoin

Senior member
Jun 1, 2017
687
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Are you sure AMD will release a product like that based on Zen2? The only existing Athlons in AMD's post-Zen family are the 200/220/240GE which are based on Raven Ridge, not Summit Ridge or Pinnacle Ridge. If AMD is going to release another set of Athlon chips, I would expect them to be based on Picasso.
It certainly poses an interesting question on how AMD intends to proceed with (the monolithic) APUs. Since they are mobile/energy optimized I'd expect a 4c8t monolithic APU even on 7nm (especially if they still use 4c8t CCX). But if the desktop Ryzen indeed starts at 6c this gen that would make such APUs below bottom end budget level, something for which the Athlon branding is used. The other option, an 8c16t APU, would make it a better fit with Ryzen potentially going up to 16c32t, but wouldn't be as mobile/energy optimized and may be very unbalanced with dual channel RAM considering the 2400G's 4c8t with 11CU already hit the RAM bottleneck.
 
Apr 27, 2000
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I don't have any insider knowledge or anything like that, but I suspect that eventually they'll have some 4-core parts that are sold as a really low-end part assuming that they can't find some other use for them.
My guess is that such parts would fall under the R3 line.
 

Timorous

Senior member
Oct 27, 2008
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It seems like the next logical evolution, but the biggest impediment seems to be that the chiplet approach doesn't work quite as well for GPUs. There was some article where an interviewer asked someone at RTG about it and the gist was that AMD has looked into the approach, but found that it didn't work well for gaming. If you think about it, it's almost like SLI/Crossfire in a way since the chiplets would be small GPUs that all get hooked together. We know that SLI/Crossfire solutions have always had some overhead and that's if they worked at all. Unless AMD has some magic drivers (issues with Vega make this hard to believe) then this approach isn't going to work for a huge chunk of the market.

Of course that doesn't mean that they can't just produce a chiplet sized GPU for this part of the market and make bigger monolithic GPUs for the midrange and high-end. It would probably also necessitate some changes to the IO die as well, so you might need another separate part their as well. If they can get around that or they've just designed their desktop IO die with that in mind and have extra stuff that isn't enabled with Ryzen chips, it's not as much of an issue. It's just a matter of economics and how much extra space they waste on each multi-purpose IO die as opposed to the extra costs of having two separate produce lines.

If you have to make a separate GPU chiplet that doesn't get used anywhere else and a separate IO die that's necessary for an APU, why not just make a monolithic chip at that point? By the time AMD refreshes the mobile chips (Picasso is Zen+ on 12 nm) the 7nm process will be much more mature and capable of handling the larger monolithic die. Or maybe they want to start going to the chiplet route because they are trying to make chiplet Crossfire work seamlessly from a software perspective. Being able to do that has far bigger implications beyond APUs though, especially if it scales beyond 2 or 4 chiplet configurations. They might even do it anyway because apparently having a chiplet-based approach works fine for a lot of compute tasks, so we get chiplets for APUs and MI cards, but monolothic GPUs for gaming.
I believe the person you are quoting is suggesting that the APUs will have two dies. the Zen2 chiplet die and a GPU die with the required IO. That would be the same as the clarkdale i5-661 CPU and looks pretty doable. The other thing of note is that the extra IO you need on top of what you get with a discrete GPU is not that much so it would mean there could be the following line up.

20 CU Navi which incorporates the required IO to work as an IO die. Can be used in a Zen2 based APU or in a discrete GPU.).
40 CU Navi - discrete only so no additional IO requirements.
80 CU Navi which incorporates the required IO to work as an IO die. Can be used in the next gen consoles as well as in a discrete GPU.
Whatever replaces VEGA on the high end.

That strategy would give AMD monolithic GPUs that can also be used as part of an APU without needing to design and manufacture a specific, single die APU solution.
 

maddie

Platinum Member
Jul 18, 2010
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I think it depends on how AMD goes about testing and binning their chips. It's entirely possible that an 8-core chip that can only hit 3 GHz across all cores, could be used as a 6-core chip that can hit 4 GHz across all cores due to one or two of the cores being particularly bad.

If AMD can get more value from a 4 GHz 6-core chiplet than a 3 GHz 8-core chiplet, I think it's pretty obvious that they'll use it as a 6-core part, especially if the yields are good and there's no shortage of 8-core parts. I think that this is definitely the case in instances where there are one or two cores that are really holding the chiplet back.

Perhaps the level of testing will be increased simply because they have so many different product categories with different needs, which means spending additional resources on the binning process is likely to save them a lot of money in the long run by making sure that they utilize their chiplets as efficiently as possible.
This is the reasoning I used earlier to predict that a top 8C CPU could be produced where the 4 highest clocking cores in each chiplet will be chosen to give us an ultra binned 8C product.

Binned chiplets and then a further bin within the chiplet itself. I can see an 8C with at least a several hundred MHz advantage over a straight single chiplet 8C. Greater IF bandwidth/core is an added advantage.

Perhaps for a 50th anniversary edition.
 

jpiniero

Diamond Member
Oct 1, 2010
6,184
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I believe the person you are quoting is suggesting that the APUs will have two dies. the Zen2 chiplet die and a GPU die with the required IO. That would be the same as the clarkdale i5-661 CPU and looks pretty doable. The other thing of note is that the extra IO you need on top of what you get with a discrete GPU is not that much so it would mean there could be the following line up.
That would make a ton of sense, but because of the WSA I have to wonder if they are going to keep the IO die at 12 nm, and it looks like it would need to be on 7 (SS7?) to fit. I guess it's not clear how many wafers AMD has to buy in order to satisfy it.

In theory, putting the GPU on the IO die would allow them to use it for a Ryzen refresh later too.
 

Timorous

Senior member
Oct 27, 2008
366
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That would make a ton of sense, but because of the WSA I have to wonder if they are going to keep the IO die at 12 nm, and it looks like it would need to be on 7 (SS7?) to fit. I guess it's not clear how many wafers AMD has to buy in order to satisfy it.

In theory, putting the GPU on the IO die would allow them to use it for a Ryzen refresh later too.
Depending on the WSA it might be fulfilled by just desktop and server IO Dies which means GPU/IO hybrids could be built at 7nm.
 
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The thing about the WSA is that each new IO die is a fair bit smaller than the full Zen+ die, so they'll get more per wafer. However, if their sales volume doesn't ramp up due to Zen 2 being incredibly competitive, they'll still be paying for a whole bunch of wafers that they weren't able to translate into sales.
Zen 2 demand should be high enough to ensure that AMD do spread their wafer cost as widely as possible, but at this point I don't think that it is guaranteed.
 

Veradun

Senior member
Jul 29, 2016
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The thing about the WSA is that each new IO die is a fair bit smaller than the full Zen+ die, so they'll get more per wafer. However, if their sales volume doesn't ramp up due to Zen 2 being incredibly competitive, they'll still be paying for a whole bunch of wafers that they weren't able to translate into sales.
Zen 2 demand should be high enough to ensure that AMD do spread their wafer cost as widely as possible, but at this point I don't think that it is guaranteed.
An EPYC2 IOdie is about four times as big as a single Zeppelin die. Meaning same "14nm footprint" of any EPYC1 SKU :>
 

Mopetar

Diamond Member
Jan 31, 2011
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This is the reasoning I used earlier to predict that a top 8C CPU could be produced where the 4 highest clocking cores in each chiplet will be chosen to give us an ultra binned 8C product.

Binned chiplets and then a further bin within the chiplet itself. I can see an 8C with at least a several hundred MHz advantage over a straight single chiplet 8C. Greater IF bandwidth/core is an added advantage.

Perhaps for a 50th anniversary edition.
That's certainly possible. It is easier to get 4 cores that clock exceptionally high as opposed to 8, as well as much easier to cool if you're throwing a lot of voltage at it. The issue is that you have to look at what has to be sacrificed and what you can expect to gain.

If it's a matter of taking some functional 8 or 6-core chiplets that could go into a $350+ CPU and disabling cores so that AMD could sell a $300 CPU, I don't see them doing it. Maybe in small quantities just for bragging rights, but not as a volume product.

They also have the option of waiting for enough suitable chiplets that can't be used as 8 or 6-core parts to accumulate. I could see them holding off on some top bin parts as a response for whatever Intel launches next.
 

dlerious

Senior member
Mar 4, 2004
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It's not just possible it positively the case. Yields will be tighter but they are getting probably more than double the working cores per wafer then they were getting before. AMD is going to be down binning chips quickly and maybe out of the gate. Which circles back to the questions regarding expensive 16c AM4 chips. It's in AMD's best interest to sell as many of the 8c dies as 8c dies as possible rather than binning down. That includes making a 16c Ryzen 3k attainable and not a small volume CPU. Selling a 16c Ryzen at $500 is going to be more profitable then down binning them into 2 6c Ryzen's selling @ <$200. Specially when you include needing 2 IO dies in that sale.
Do you mean 2 chiplets instead of 2 I/O dies? I don't think they're going to be selling a 12-core for less than $200. I'd guess $299 at lowest.
 

Topweasel

Diamond Member
Oct 19, 2000
4,742
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Do you mean 2 chiplets instead of 2 I/O dies? I don't think they're going to be selling a 12-core for less than $200. I'd guess $299 at lowest.
The questions regarding the existence of a 16c chip or it's price being $700+ is going to leave a 12c option pretty expensive as well or also non existant. My point was that AMD inevitably and probably right away down bin 8c chiplets into 6c ones. So if there is a single chiplet 6c CPU, many of them will be fully working dies. It's in AMDs best interest to sell as many 16c and 8c chips as possible even if the 16c chip isn't twice as expensive as the 8c or even 6c CPUs. Even if it's just because the packaging cost different of not needing a second heatspeader, second PCB, and most importantly no second IO chip.

It's not just about ASP. It's not just about showing superiority over Intel. Those 8c dies are more valuable to sell as 8c chips instead of 6c or less chips. Even if that means not maximizing the ASP as absolutely high as possible.
 

RaV666

Junior Member
Jan 26, 2004
11
3
81
So, guys i have a simple question.
There was this idea about IO die containing L4 cache for matisse.We now know its size, and its 120mm2.
At first i thought "Thats pretty big for something without the cores" as zen die is 212mm2,.
Then i looked up die shot:
https://en.wikichip.org/w/images/th...px-amd_zen_octa-core_die_shot_(annotated).png

Then i used a very complicated image analysis process to analyze the ccx size called "eyeballing it" .
And i came to a conclusion that CCX`s are around 40% of the die. 212mm2-~40%=127mm2.
So it seems theres no space for L4.Am i right in this assumption ?
Also , we are pretty sure now that chiplets have 2CCX`s each right ?
 

beginner99

Diamond Member
Jun 2, 2009
4,001
122
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So, guys i have a simple question.
There was this idea about IO die containing L4 cache for matisse.We now know its size, and its 120mm2.
At first i thought "Thats pretty big for something without the cores" as zen die is 212mm2,.
Then i looked up die shot:
https://en.wikichip.org/w/images/thumb/7/75/amd_zen_octa-core_die_shot_(annotated).png/950px-amd_zen_octa-core_die_shot_(annotated).png

Then i used a very complicated image analysis process to analyze the ccx size called "eyeballing it" .
And i came to a conclusion that CCX`s are around 40% of the die. 212mm2-~40%=127mm2.
So it seems theres no space for L4.Am i right in this assumption ?
Also , we are pretty sure now that chiplets have 2CCX`s each right ?

More or less yes. However you need to keep in mind that each zeppelin die had more IO than was needed for Ryzen especially IF links to link together the 4 dies in Epyc and TR. Desktop IO die doesn't need that, 2 are enough.
 

Mopetar

Diamond Member
Jan 31, 2011
4,445
372
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Then i used a very complicated image analysis process to analyze the ccx size called "eyeballing it" .
And i came to a conclusion that CCX`s are around 40% of the die. 212mm2-~40%=127mm2.
So it seems theres no space for L4.Am i right in this assumption ?
Also , we are pretty sure now that chiplets have 2CCX`s each right ?
I used a slightly more complicated image analysis process called measuring the pixel widths and subtracting the area of CCX, and 40% is about spot on.

It's probably reasonable to assume that there's not a massive amount of L4 cache on the IO die, but that doesn't necessarily mean there couldn't be something else. I am curious if there is anything on there that hasn't been announced yet, such as the kind of IO that would be necessary if they really were going to make graphics chiplets as well. There were some posts earlier that thought it would be neat if they included a very minimal amount of GPU cores just to have bare-bones on-board video with Ryzen.
 

PPB

Golden Member
Jul 5, 2013
1,100
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AMD could do both 8 core models with one die and two dies with 4 cores each.

As for Epyc, AMD has said there will be models with less than 8 dies. They have plenty of options there. Really any multiple of 6 or 8 is possible. If TR is indeed using the Epyc IO die, I don't see why it wouldn't be possible for it to have more than 4 dies.



I don't know why people continue to defend Adored when it's obvious he is making up stuff for clicks/views. It should have been pretty obvious the 'leaked' list for Ryzen and Navi was made up.
Anandtech sure are going clickbaity by stating first time that vega VII was a 128rop card...


Oh wait, they made a mistake and admitted the error and promptly corrected it to 64 rops. It happens (and that happened going at official sources) , get over it.
 

maddie

Platinum Member
Jul 18, 2010
2,436
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More or less yes. However you need to keep in mind that each zeppelin die had more IO than was needed for Ryzen especially IF links to link together the 4 dies in Epyc and TR. Desktop IO die doesn't need that, 2 are enough.
Isn't this an assumption based on Zen 2 having the same IF bandwidth as Zen1? If it's upgraded, the new IF links might be larger than expected. It would make sense to me for AMD to go wider than faster to increase capacity if you're concerned by power usage.
 
Mar 11, 2004
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This makes me think, AMD should see if they could make HBM (its a JEDEC standard, so is there anything that would really prevent it?), so that they could integrate it into their chips. It'd let them skip the interposer, and would help with some other packaging issues (difference in heights of chips). And they could keep things fairly simple, as even a single high stack would probably still do wonders for their monolithic APUs (while not being excessively complex). They could stack it or have it side by side. And probably the best would be integrating it with the I/O die.

What process is HBM/2 made on?

I believe the person you are quoting is suggesting that the APUs will have two dies. the Zen2 chiplet die and a GPU die with the required IO. That would be the same as the clarkdale i5-661 CPU and looks pretty doable. The other thing of note is that the extra IO you need on top of what you get with a discrete GPU is not that much so it would mean there could be the following line up.

20 CU Navi which incorporates the required IO to work as an IO die. Can be used in a Zen2 based APU or in a discrete GPU.).
40 CU Navi - discrete only so no additional IO requirements.
80 CU Navi which incorporates the required IO to work as an IO die. Can be used in the next gen consoles as well as in a discrete GPU.
Whatever replaces VEGA on the high end.

That strategy would give AMD monolithic GPUs that can also be used as part of an APU without needing to design and manufacture a specific, single die APU solution.
That would be an interesting route. My issue with that is I doubt they do that on 7nm initially, so we'd be looking at them using Vega for the GPU since I doubt they backport Navi to 12nm (they'd just wait til they were ready to do something like that on 7nm). I have a hunch their 7nm plans this year is more limited than people think, and that would be Vega 20 (which I'd wonder if it stays in production once Navi starts production), Zen 2 die, and Navi (which I won't be surprised if its just a single chip this year since that would be enough for its intended market with just binned/defective ones going to the different tiers).

Maybe they'd add Polaris or Vega CUs to the I/O die. That would actually be ok. It'd let them offer improved performance and efficiency (the lower power CPU would enable more GPU headroom) in APUs (where you'd have some GPU, but with a Zen 2 die, you'd also do well with a dGPU so they could upsell that aspect where then you'd have the CPU less constrained as the dGPU would mean the iGPU wouldn't need headroom). Then next year they do Navi based, where it brings worthwhile improvements from just updating the GPU.

Now, in places they'd do different package (like say mobile? I'm not sure what they do for chips there), they could do something different. But I kinda doubt Navi will have HBM memory controller, so I kinda doubt we'd see anything too interesting there (like Vega M thing with Intel), but then Zen 2 and Navi as discrete would do well in laptops. Weirdly, I'm getting the impression that AMD doesn't have much plans for Zen 2 and Navi in mobile yet, with them probably waiting til next year for that. But I think they'd be crazy to not have OEMs do that for gaming laptops where it'd offer good performance.

I don't know though, as I'm expecting to get a Zen 2+ thing next year, and then Zen 3 with AM5, but AMD acts like Zen 3 might be next year. Not sure if they're trying to catch Intel on Xth gen Core type stuff or what so they're just calling every new series Zen X regardless of it being substantially different.

That would make a ton of sense, but because of the WSA I have to wonder if they are going to keep the IO die at 12 nm, and it looks like it would need to be on 7 (SS7?) to fit. I guess it's not clear how many wafers AMD has to buy in order to satisfy it.

In theory, putting the GPU on the IO die would allow them to use it for a Ryzen refresh later too.
I would guess they change the packaging before they fit a separate GPU die on, unless its a small one or is a change to the I/O die (which I think wouldn't be 7nm, so it'd be using older GPU for now). Without substantial change to memory config, it would be almost completely pointless for a larger GPU, and so you have to not only fit the GPU die, be concerned with I/O fitting, but also probably make space for HBM on the package (which then you'll probably be talking about some form of interposer, further cramping your space).

I guess we'll see what size Navi comes in at, and perhaps this might give some indication on size, but hopefully not as I think that would be awfully restrictive (and I can't imagine such a small GPU, even on 7nm, would be able to meet their performance goals). Zen 2 chip is what ~80mm2? If Polaris was shrunk and got the full 2x density improvement, that'd still be almost 50% larger than a Zen 2 die. And they really don't have the space for that, so anything beyond what 24CU wouldn't be feasible. But even that would be more GPU than the memory bandwidth would be able to really supply.

I think until AM5, we'd at best get a small GPU. Now, they could use Threadripper package/socket til then, which would give them extra power/thermal headroom (they'd be able to have like 45-65W CPU, 100-150W GPU, the I/O die, and then even probably like 8GB of HBM2 memory), and Threadripper's extra memory channels would be helpful. Maybe they could even make a special I/O die with large cache or something that would make it so they wouldn't need HBM. But that would only be for some special premium products, and most of those would probably be better with just Zen 2 CPU, and dGPU Navi, and that would be cheaper.

AM5 should hopefully make it more feasible, if for no other reason than it would enable extra memory channels and DDR5 would bring more bandwidth as well. I hope AMD is thinking about potential packaging as they develop AM5 though, so they design it for maximizing chiplets potential.
 

dlerious

Senior member
Mar 4, 2004
647
27
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The questions regarding the existence of a 16c chip or it's price being $700+ is going to leave a 12c option pretty expensive as well or also non existant. My point was that AMD inevitably and probably right away down bin 8c chiplets into 6c ones. So if there is a single chiplet 6c CPU, many of them will be fully working dies. It's in AMDs best interest to sell as many 16c and 8c chips as possible even if the 16c chip isn't twice as expensive as the 8c or even 6c CPUs. Even if it's just because the packaging cost different of not needing a second heatspeader, second PCB, and most importantly no second IO chip.

It's not just about ASP. It's not just about showing superiority over Intel. Those 8c dies are more valuable to sell as 8c chips instead of 6c or less chips. Even if that means not maximizing the ASP as absolutely high as possible.
Maybe the cold weather is affecting me, but I still don't understand why they'd have a second heatspreader, PCB, or I/O chip. I would've assumed they'd use a dummy die for single chipet products and designed the PCB in such a way that it could be used with either 1 or 2 chiplets.
 

Shivansps

Platinum Member
Sep 11, 2013
2,425
173
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20 CU Navi which incorporates the required IO to work as an IO die. Can be used in a Zen2 based APU or in a discrete GPU.).
Im certain that, if that thing exist it will be a DDR5 only APU.

Im expecting as best case scenario a Vega 8 in current DDR4 i/o.
 


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