Speculation: Ryzen 3000 series

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What will Ryzen 3000 for AM4 look like?


  • Total voters
    182

amd6502

Senior member
Apr 21, 2017
450
53
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Yeah I also don't see this 2 times 4 cores happening for 8 core AM4 CPUs
I assume the same ratio of yield they had with 8 core zeppelin.
I see both 4c single chiplet and 4c+4c double chiplet for low binned SKU below the 8c single chiplet.

Although the dies are small, I don't see the 7nm yields being nearly as good as their previous nodes. It wouldn't surprise me if we even saw 2c+2c lower Ryzen 3 binning, although that would take some time to accumulate, and would hit in 2020.
 

amd6502

Senior member
Apr 21, 2017
450
53
61
Don't pretend that you don't know you could describe exactly how and why do you say these things about him, without having to 'link' a video or 'supporting' him (with what exactly?)... I honestly don't care if you don't like his business model, the world is beautiful because we are all different. But avoiding an explanation at any cost after your wildly thrown general accusations towards him, is kindergarten for me.
Wasting other people's time and feeling entitled like this means never having graduated from kindergarten.

PS

Confirmed, the video is titled exactly as recalled, video dated Dec 4.
 
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amd6502

Senior member
Apr 21, 2017
450
53
61
Personally I still think there is perfectly enough room for both a power optimized monolithic low end APU with up to 4 cores where the uncore is cut down to the bare necessary amount as well as a IOC/chiplet/GPUlet MCM that goes up to 8 cores and has all the standard AM4 IO to exist alongside. But it may well be the case the platform and/or IOC is not prepared for the latter.
It makes sense to stagger the MCM and monolithic products. Monolithic is ideally during the optimization turn. Inflection (Zen, SR followed by RR) -> Optimization (Zen+, PR followed by Picasso) -> Inflection (Zen2 MCM, cpu** followed by apu) -> Optimization (Zen2/3, monolithic APU) https://community.amd.com/thread/226363

**: cpu possibly with lite igpu.

 
Feb 23, 2017
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These last bunch of pages have been a really tough read.
I'm not really a great fan of censorship, however, 70% of the posts I just read were either juvenile or responses to juvenile comments. Surely there must be a way of banning folk solely from particular threads...? They're clearly not willing to self-regulate, though I don't think a whole forum-wide ban necessary for single thread infringement/trolling/hatred.

*******

I mentioned a while back that there might have been a case for non-X SKUs to be harvested chiplets. These SKUs are likely to be higher sales volume, lower performance, lower price, much like how the 2600 is the leading seller right now. Ultimately though, I agree with others that this can only really be the case if chiplet yields aren't great. The problem I have with the idea that yields being so low is that it'd imply that the whole chiplet strategy was a house of cards; a revolutionary design is only great if it is economically viable, and not a white elephant like Concorde.
I also like the concept of Rome using the defective chiplets, since we can be certain that those SKUs would come with much higher margins regardless of configuration. A 32c Rome with 8x 4 functional cores makes more sense than 4x R5 3500 made of 2x 4 functional cores.
 
Dec 10, 2018
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I see both 4c single chiplet and 4c+4c double chiplet for low binned SKU below the 8c single chiplet.

Although the dies are small, I don't see the 7nm yields being nearly as good as their previous nodes. It wouldn't surprise me if we even saw 2c+2c lower Ryzen 3 binning, although that would take some time to accumulate, and would hit in 2020.
The problem I have with the idea that yields being so low is that it'd imply that the whole chiplet strategy was a house of cards;
For perspective, Apple's A12 chip uses the exact same process with almost the same die area as a chiplet. Shallow searching didn't turn up anything on how much Apple bins, or how much redundancy they put into their chip, but their relatively high standards for hardware gives me the impression that 7nm yields aren't anywhere close to bad enough that half the die would need to be disabled on a significant number of chiplets.

I would bet seeing segmentation based off 6 and 8 core chiplets.

6/12/8/16 core Ryzen
24/32/48/64 core Rome
24/32 core TR?

Maybe they'll release lower end versions if yield really is that bad? Or maybe after they've stockpiled enough.
 

lobz

Senior member
Feb 10, 2017
232
40
86
So what exactly in dispute? Are you claiming Adored TV doesn't call his information "leaks"? I thought that was pretty well established that he does.
See what you do again? You pretend like you didn't get what we say and start immediately picking on singled out words. I'm gonna just let you win. Maybe we can then go further on topic, which is Ryzen 3000 series SPECULATION.
 

lobz

Senior member
Feb 10, 2017
232
40
86
Wasting other people's time and feeling entitled like this means never having graduated from kindergarten.

PS

Confirmed, the video is titled exactly as recalled, video dated Dec 4.
I was scratching my head for the last 10 minutes, but I still can't for the life of me figure out, exactly where am I feeling entitled. I mean I know I don't, I just wanted to see what could have given you the impression after all.
 

Atari2600

Senior member
Nov 22, 2016
724
169
106
I mentioned a while back that there might have been a case for non-X SKUs to be harvested chiplets. These SKUs are likely to be higher sales volume, lower performance, lower price, much like how the 2600 is the leading seller right now. Ultimately though, I agree with others that this can only really be the case if chiplet yields aren't great. The problem I have with the idea that yields being so low is that it'd imply that the whole chiplet strategy was a house of cards; a revolutionary design is only great if it is economically viable, and not a white elephant like Concorde.
Regardless of yields, the chiplet strategy is more efficient I think.

Good yields:
- getting more per wafer due to better edges
- saving money on non-value adding I/O into 7nm

Bad yields:
<All as mentioned for good yields plus>
- far easier to get better yields on a small chip than a big one
- far easier to package up what good chips you do have to cover various market points.


Either way, AMD get more out of 7nm by moving off-socket I/O away from the cores.


I also like the concept of Rome using the defective chiplets, since we can be certain that those SKUs would come with much higher margins regardless of configuration. A 32c Rome with 8x 4 functional cores makes more sense than 4x R5 3500 made of 2x 4 functional cores.
I'd say whether EYPC sees defective chiplets would depend on how strained capacity is and how power efficient the "bad" bins are.
 

Topweasel

Diamond Member
Oct 19, 2000
4,742
345
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Personally. Bad yields or not if AMD is getting a decent wafer allotment from TSMC they will be swimming in good chips. I have a distinct feeling that Eypc and TR will both have 4 chiplet variations, hell TR I give them a 50% chance of only being 4 die versions of Epyc. Because of how the chiplets are wired they should be able to do this without any kind of performance impact, good or bad. Doing 4 chips will allow them to offer higher clocks for server solutions that prefer clockspeed over computational power (tools that you license by the core and such).
 

maddie

Platinum Member
Jul 18, 2010
2,436
358
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See what you do again? You pretend like you didn't get what we say and start immediately picking on singled out words. I'm gonna just let you win. Maybe we can then go further on topic, which is Ryzen 3000 series SPECULATION.
Sorry for turning the thread into a cesspit, I won't do that again.
Good responsible posts.

Took a nap yesterday and returned to find this thread in flames. Good to see normalcy returned. Provided some laughs though. Peace all.
 

DarthKyrie

Senior member
Jul 11, 2016
454
287
116
For perspective, Apple's A12 chip uses the exact same process with almost the same die area as a chiplet. Shallow searching didn't turn up anything on how much Apple bins, or how much redundancy they put into their chip, but their relatively high standards for hardware gives me the impression that 7nm yields aren't anywhere close to bad enough that half the die would need to be disabled on a significant number of chiplets.

I would bet seeing segmentation based off 6 and 8 core chiplets.

6/12/8/16 core Ryzen
24/32/48/64 core Rome
24/32 core TR?

Maybe they'll release lower end versions if yield really is that bad? Or maybe after they've stockpiled enough.
Just so you know TSMC has 2 versions of 7nm, they have the regular 7nm that they developed and then they have 7HPC which AMD assisted on. Apple is using regular 7nm and AMD is using 7HPC for obvious reasons.
 

mattiasnyc

Senior member
Mar 30, 2017
311
142
106
So what exactly in dispute? Are you claiming Adored TV doesn't call his information "leaks"? I thought that was pretty well established that he does.
It's pretty disingenuous of you to go down this path.

First of all you have to consider what the term means and secondly what the implications are. The term "leak" which he indeed uses implies that someone with knowledge that shouldn't be shared is sharing knowledge anyway. So if someone is working for AMD or a subcontractor is sitting on confidential information and emails Jim and shares some of that info then that's indeed a leak.

Secondly, just because that person shares that information doesn't mean that it will remain true in eternity. That person may have shared information in October or whatever, and the company may have changed direction in December. Now what? Was the information retroactively false? Of course not. It was true at the time. It's as if you tell me that you're going to the gym, and you have the intention of doing so. But then there's a family emergency and you choose to not go. If I tell someone that you're going to the gym before the emergency phone call comes in am I now a liar retroactively? Did I spread rumors instead of facts?

That's why this is a disingenuous conversation on your part.

On top of that, if you are going to accuse him of calling "rumors" "leaks", then you need to actually know that his sources where just rumors and not actual leaks. Of course you don't know that, you simply assume that a person can never ever leak any information after which something changes (as I mentioned above). A rumor is pretty much just reading speculation or unsubstantiated facts online (or somewhere) and then spreading that further. It's a completely different matter.

And I reiterate that anyone who thinks the phrase "take this with a pinch of salt" means nothing and then proceeds to take something at face value is... well... 'clueless' is a decent word I think...

... but then again these days "fake" means just as little as "global warming" or "crisis" or whatever...
 

LightningZ71

Senior member
Mar 10, 2017
238
6
86
So, what are we guessing the R3XXX product stack will look like?

With the way that AMD has, in the past, configured their CPUs, they will likely have recovered chiplets in 6, 4 and 2 operational core versions. The question is, is there sufficient cost recovery in reusing the chiplets that have only 2 working cores? In anything other than the TR and EPYC, they are better served by using the Picasso chips at 4 cores to serve that market.

We have the 2 chiplet versions in 2 X 8 core, high clocked, and 2 X 8 core low clocked as well as 2 X 6 core high clock and 2 X 6 core low clock. Will we also see 2 X 4 core high clock and 2 X 4 core low clock as well as 2 X 2 core in high clock and low clock in OEM parts? Then, there are the single chip version in 1 X 8 core and 1 X 6 core?

Here's my guess:
For the R3800X, they will use 2 X 8 cores that clock well, likely only thermally and power limited. 64 MB L3
For the R3800, its 2 X 8 cores that don't clock as well, no PBO 64 MB L3
For the R3700X, they will use 2 X 6 core chiplets that clock extremely well. This will likely be the single thread champion in the 2 chiplet group. It'll also likely give some of the best memory throughput numbers per thread with having 64 MB of L3 feeding 24 threads.
For the R3700, they will use 2 X 6 core chiplets, lower clocks, no PBO 64 MB L3
For the R3600X, it'll be a single 8 core chiplet at full performance 32 MB L3
For the R3600, it'll be a single 8 core chiplet at reduced clock, no PBO 32MB L3
For the R3500X, it'll be a single 6 core chiplet at full performance 32 MB L3
For the R3500, it'll be a single 6 core chiplet at reduced performance. 32 MB L3
For the R3400, there will be the R3400G at 4 cores, 8 threads, APU 4 MB L3
For the R3300, there will be the R3300G at 4 cores, 8 threads, with a reduced clock and reduced GPU CU count 4 MB L3
For the R3200, there will be the R3200G with 4 cores, 4 threads, reduced GPU CU count 4 MB L3
Then there's the Athlon 300/320/340 at 2 cores, 4 threads, differing clocks. 4 MB L3
This also leaves room for a R3400X OEM chip that uses 2 X 2 core chiplets with PBO if yields on working cores for chiplets are bad. 32 MB L3

So, where do the 4 core and 2 core recovery chiplets go? Epyc and Threadripper. The only functional internal difference between them will be the number of working DRAM channels. TR3 will essentially be only EPYCs that have a failed DDR channel.
I'm thinking that there will be a TR3 lineup like so:
3920 - 8 X 2 core chiplet, 16 cores, likely half L3 cache at 128 MB
3950 - 8 X 4 core chiplet, 32 cores, 256 MB L3
3970 - 8 X 6 core chiplet, 48 cores 256 MB L3
3990 - 8 X 8 core chiplet, 64 cores 256 MB L3

All but the 3990 are using recovered chiplets. The 3990 will be a premium product and will command a high price because of it, justifying using the precious 8 core chiplets. The lower end TR3 line can certainly use the volume of 2 and 4 core chiplets if yields are reasonably good, and still get a premium from them. The EPYC can also do the same. As time moves on, and yields improve, if the mix of 8 core chiplets is just extreme, then AMD can shift production to using the fewest number of chiplets like so

3910 - 2 X 8 core chiplets, 16 cores full cache, 64 MB L3
3940 - 4 X 8 core chiplets, 32 cores full cache, 128 MB L3
3960 - 6 X 8 core chiplets, 48 cores full cache, 192MB L3

All this assumes that the information on the chiplets having 32MB of L3 is true. Halve the numbers if it isn't.

I know this is all speculation, but it looks like a solid product stack to me, and also an extremely competitive one with anything Intel will be offering.
 

PeterScott

Platinum Member
Jul 7, 2017
2,605
226
96
It's pretty disingenuous of you to go down this path.

First of all you have to consider what the term means and secondly what the implications are. The term "leak" which he indeed uses implies that someone with knowledge that shouldn't be shared is sharing knowledge anyway. So if someone is working for AMD or a subcontractor is sitting on confidential information and emails Jim and shares some of that info then that's indeed a leak.

Secondly, just because that person shares that information doesn't mean that it will remain true in eternity. That person may have shared information in October or whatever, and the company may have changed direction in December. Now what? Was the information retroactively false? Of course not. It was true at the time. It's as if you tell me that you're going to the gym, and you have the intention of doing so. But then there's a family emergency and you choose to not go. If I tell someone that you're going to the gym before the emergency phone call comes in am I now a liar retroactively? Did I spread rumors instead of facts?

That's why this is a disingenuous conversation on your part.

On top of that, if you are going to accuse him of calling "rumors" "leaks", then you need to actually know that his sources where just rumors and not actual leaks. Of course you don't know that, you simply assume that a person can never ever leak any information after which something changes (as I mentioned above). A rumor is pretty much just reading speculation or unsubstantiated facts online (or somewhere) and then spreading that further. It's a completely different matter.

And I reiterate that anyone who thinks the phrase "take this with a pinch of salt" means nothing and then proceeds to take something at face value is... well... 'clueless' is a decent word I think...

... but then again these days "fake" means just as little as "global warming" or "crisis" or whatever...
It's not disingenuous to offer my opinion that these so called "leaks" are really rumors and speculation.
 

Markfw

CPU Moderator, VC&G Moderator, Elite Member
Super Moderator
May 16, 2002
17,363
755
136
It's not disingenuous to offer my opinion that these so called "leaks" are really rumors and speculation.
This is a SPECULATION thread what do you expect, now stop talking about that, and stay on-topic.
 

jpiniero

Diamond Member
Oct 1, 2010
6,184
172
126
So, where do the 4 core and 2 core recovery chiplets go?
AMD could do both 8 core models with one die and two dies with 4 cores each.

As for Epyc, AMD has said there will be models with less than 8 dies. They have plenty of options there. Really any multiple of 6 or 8 is possible. If TR is indeed using the Epyc IO die, I don't see why it wouldn't be possible for it to have more than 4 dies.

There are good and bad leaks. Adored got a bad one this time. Move on.
I don't know why people continue to defend Adored when it's obvious he is making up stuff for clicks/views. It should have been pretty obvious the 'leaked' list for Ryzen and Navi was made up.
 
Nov 7, 2018
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I've seen some fellow members point out "yields must be bad" if AMD needs to use lots of "defective" chiplets for their Zen 2 chips but that may not necessarily be the case:

Screenshot from 2019-01-29 17-36-06.png

For the purposes of the above pic's example, let's assume AMD will make 3 CPUs with 12 cores (two chiplets) @ 2.2 GHz, 2.6 GHz, and 3 GHz. It's quite possible to have a fully functioning 8 core chiplet to be used with 6 / 12 core CPU: all it needs is lower clock speed on some of the cores (than intended for the CPU), and those cores can be fused off.

What i'm trying to say is that it's possible for AMD to use fully functioning chiplets in lower segmentation (than 8 / 16 cores) without it being because of bad yields.
 

Topweasel

Diamond Member
Oct 19, 2000
4,742
345
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I've seen some fellow members point out "yields must be bad" if AMD needs to use lots of "defective" chiplets for their Zen 2 chips but that may not necessarily be the case:

View attachment 2875

For the purposes of the above pic's example, let's assume AMD will make 3 CPUs with 12 cores (two chiplets) @ 2.2 GHz, 2.6 GHz, and 3 GHz. It's quite possible to have a fully functioning 8 core chiplet to be used with 6 / 12 core CPU: all it needs is lower clock speed on some of the cores (than intended for the CPU), and those cores can be fused off.

What i'm trying to say is that it's possible for AMD to use fully functioning chiplets in lower segmentation (than 8 / 16 cores) without it being because of bad yields.
It's not just possible it positively the case. Yields will be tighter but they are getting probably more than double the working cores per wafer then they were getting before. AMD is going to be down binning chips quickly and maybe out of the gate. Which circles back to the questions regarding expensive 16c AM4 chips. It's in AMD's best interest to sell as many of the 8c dies as 8c dies as possible rather than binning down. That includes making a 16c Ryzen 3k attainable and not a small volume CPU. Selling a 16c Ryzen at $500 is going to be more profitable then down binning them into 2 6c Ryzen's selling @ <$200. Specially when you include needing 2 IO dies in that sale.
 
Jan 17, 2019
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Those "defective" parts which are still usable for something probably are not counted as defective in yield calculation.
 
Jan 17, 2019
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BTW AMD could have revealed MUCH more about Ryzen 3000 series without actually causing any damage (concerning competition with Intel etc.). If they did not reveal processor frequencies, core counts and power consumption, Intel cannot be sure what exact processors will hit the market. This information vacuum is really tiring.
 

inf64

Platinum Member
Mar 11, 2011
2,814
35
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crazyworldofchips.blogspot.com
BTW AMD could have revealed MUCH more about Ryzen 3000 series without actually causing any damage (concerning competition with Intel etc.). If they did not reveal processor frequencies, core counts and power consumption, Intel cannot be sure what exact processors will hit the market. This information vacuum is really tiring.
Intel knows very well what SKUs and core counts AMD will release in 2019 :).
 

Topweasel

Diamond Member
Oct 19, 2000
4,742
345
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Those "defective" parts which are still usable for something probably are not counted as defective in yield calculation.
Depends on how it is being stated. But generally with out any qualifiers it refers to chip that are fully capable where fully capable is judged by it's requirements.

Example being Raven Ridge that was only ever available with at least one CU disabled. This was done to lift the yields up by considering all chips that were capable of I think 11 to 12 or 10-11 (can't remember the actual count) were "fully functional". There is some evidence with the "Starship" roadmap that AMD intended originally to only use 6c out of the 8c due to possible yield issues on 7nm. So not counting binning now all 8c have to be working to be fully functional.

From there you can increase the practical yields by binning for speed and cores.

But I still expect AMD to be down binning and fusing off cores on fully functional dies.
 
Apr 27, 2000
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What i'm trying to say is that it's possible for AMD to use fully functioning chiplets in lower segmentation (than 8 / 16 cores) without it being because of bad yields.
Has anyone confirmed whether "good" 8c dice were used in the production of Zen CPUs like the R5 1600x? It certainly seems to me that it was a possibility then, and it may be a possibility now with Zen2.
 


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