This makes me think, AMD should see if they could make HBM (its a JEDEC standard, so is there anything that would really prevent it?), so that they could integrate it into their chips. It'd let them skip the interposer, and would help with some other packaging issues (difference in heights of chips). And they could keep things fairly simple, as even a single high stack would probably still do wonders for their monolithic APUs (while not being excessively complex). They could stack it or have it side by side. And probably the best would be integrating it with the I/O die.
What process is HBM/2 made on?
I believe the person you are quoting is suggesting that the APUs will have two dies. the Zen2 chiplet die and a GPU die with the required IO. That would be the same as the clarkdale i5-661 CPU and looks pretty doable. The other thing of note is that the extra IO you need on top of what you get with a discrete GPU is not that much so it would mean there could be the following line up.
20 CU Navi which incorporates the required IO to work as an IO die. Can be used in a Zen2 based APU or in a discrete GPU.).
40 CU Navi - discrete only so no additional IO requirements.
80 CU Navi which incorporates the required IO to work as an IO die. Can be used in the next gen consoles as well as in a discrete GPU.
Whatever replaces VEGA on the high end.
That strategy would give AMD monolithic GPUs that can also be used as part of an APU without needing to design and manufacture a specific, single die APU solution.
That would be an interesting route. My issue with that is I doubt they do that on 7nm initially, so we'd be looking at them using Vega for the GPU since I doubt they backport Navi to 12nm (they'd just wait til they were ready to do something like that on 7nm). I have a hunch their 7nm plans this year is more limited than people think, and that would be Vega 20 (which I'd wonder if it stays in production once Navi starts production), Zen 2 die, and Navi (which I won't be surprised if its just a single chip this year since that would be enough for its intended market with just binned/defective ones going to the different tiers).
Maybe they'd add Polaris or Vega CUs to the I/O die. That would actually be ok. It'd let them offer improved performance and efficiency (the lower power CPU would enable more GPU headroom) in APUs (where you'd have some GPU, but with a Zen 2 die, you'd also do well with a dGPU so they could upsell that aspect where then you'd have the CPU less constrained as the dGPU would mean the iGPU wouldn't need headroom). Then next year they do Navi based, where it brings worthwhile improvements from just updating the GPU.
Now, in places they'd do different package (like say mobile? I'm not sure what they do for chips there), they could do something different. But I kinda doubt Navi will have HBM memory controller, so I kinda doubt we'd see anything too interesting there (like Vega M thing with Intel), but then Zen 2 and Navi as discrete would do well in laptops. Weirdly, I'm getting the impression that AMD doesn't have much plans for Zen 2 and Navi in mobile yet, with them probably waiting til next year for that. But I think they'd be crazy to not have OEMs do that for gaming laptops where it'd offer good performance.
I don't know though, as I'm expecting to get a Zen 2+ thing next year, and then Zen 3 with AM5, but AMD acts like Zen 3 might be next year. Not sure if they're trying to catch Intel on Xth gen Core type stuff or what so they're just calling every new series Zen X regardless of it being substantially different.
That would make a ton of sense, but because of the WSA I have to wonder if they are going to keep the IO die at 12 nm, and it looks like it would need to be on 7 (SS7?) to fit. I guess it's not clear how many wafers AMD has to buy in order to satisfy it.
In theory, putting the GPU on the IO die would allow them to use it for a Ryzen refresh later too.
I would guess they change the packaging before they fit a separate GPU die on, unless its a small one or is a change to the I/O die (which I think wouldn't be 7nm, so it'd be using older GPU for now). Without substantial change to memory config, it would be almost completely pointless for a larger GPU, and so you have to not only fit the GPU die, be concerned with I/O fitting, but also probably make space for HBM on the package (which then you'll probably be talking about some form of interposer, further cramping your space).
I guess we'll see what size Navi comes in at, and perhaps this might give some indication on size, but hopefully not as I think that would be awfully restrictive (and I can't imagine such a small GPU, even on 7nm, would be able to meet their performance goals). Zen 2 chip is what ~80mm2? If Polaris was shrunk and got the full 2x density improvement, that'd still be almost 50% larger than a Zen 2 die. And they really don't have the space for that, so anything beyond what 24CU wouldn't be feasible. But even that would be more GPU than the memory bandwidth would be able to really supply.
I think until AM5, we'd at best get a small GPU. Now, they could use Threadripper package/socket til then, which would give them extra power/thermal headroom (they'd be able to have like 45-65W CPU, 100-150W GPU, the I/O die, and then even probably like 8GB of HBM2 memory), and Threadripper's extra memory channels would be helpful. Maybe they could even make a special I/O die with large cache or something that would make it so they wouldn't need HBM. But that would only be for some special premium products, and most of those would probably be better with just Zen 2 CPU, and dGPU Navi, and that would be cheaper.
AM5 should hopefully make it more feasible, if for no other reason than it would enable extra memory channels and DDR5 would bring more bandwidth as well. I hope AMD is thinking about potential packaging as they develop AM5 though, so they design it for maximizing chiplets potential.