Discussion RDNA 5 / UDNA (CDNA Next) speculation

[marees]

When we would actually expect to see next-gen Nvidia Rubin or AMD RDNA 5 is surely going to be 2027 at this point - and if RTX 50-series Super is delayed (Nvidia will argue that it hasn't announced anything, therefore there is no delay) and arrives in, say, Q3 2026, we would expect that to push back Rubin until much later into 2027.

Graphics innovation drives the PC gaming market and updates to existing lines could be a long way off, let alone true next-gen upgrades. How long really depends on what 3nm inventory AMD and Nvidia have secured from chip manufacturer TSMC and if memory is available at a reasonable price to make a sizeable roll-out possible.

https://www.digitalfoundry.net/news/2025/12/the-ai-tech-crunch-are-we-looking-at-a-dark-age-for-gaming-hardware

 

[Win2012R2]

and arrives in, say, Q3 2026

It won't because memory prices will be super high at least all of 2026, it's far more sensible for Nvidia to use GDDR7 for their Rubin CPX thingy.

AMD's unique chance is to launch RDNA 5 next year, hope they don't squander it.

 

[basix]

Being stuck with Clamshell the entire generation would be rough.

I'm sure IO is going to be mega expensive on N3... but I would much rather do 256-bit without clamshell to get the extra memory bandwidth.

Well, maybe it is simply not required to have more memory bandwidth:
- Revamped CUs and respective low level caches (bigger capacity)
- Out-of-order execution (increase hardware utilization of ALUs and cache)
- Maybe L0 cache sharing across multiple CUs (reduce wasted SRAM capacity, reduce LLC & DRAM bandwidth requirements)
- Universal compression (smaller memory footprint, reduce bandwidth requirements)
- DGF & DMM (smaller memory footprint, reduce bandwidth requirements)
- Neural techniques like NTC which aim to reduce data fetching from DRAM but rather use more compute from matrix engines (whose performance mostly rely on CU low level caches) to generate or extract data and information
- Work graphs and procedural algorithms with dynamic execution on CU level (reduces code footprints and reduces bandwidth pressure from higher level caches and DRAM)

All those things aim to maximize usage of low level CU resources, increase data locality and reduce load on higher level structures like LLC and DRAM.
It seems that there is much going on regarding rethinking GPU architecture as a whole.

 

[Win2012R2]

What is the usage of 36Gbps memory die beside RDNA5?

It's for Rubin CPX

 

[basix]

As 42 Gbps and 48 Gbps are already announced: Wouldn't Rubin CPX benefit from more bandwidth?

For gaming I do not see bandwidth demands at these levels. 32...36 Gbps seem to be fine on e.g. a 512bit 6090 or AMDs equivalent based on AT0.

 

[adroc_thurston]

As 42 Gbps and 48 Gbps are already announced: Wouldn't Rubin CPX benefit from more bandwidth?

yes and no.
prefill is compute-bound, that's why they're even using an HBMless part anywhere GPGPU.