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Channels are the limiting factor.....but there also needs to be enough Gen 1 dies to fill the 300 MB/s capacity of each channel.
No, they talked about this during Optane launches. I don't know why you are suddenly changing altogether. NAND needs multiple dies to saturate channel because the media is slow. 3D XPoint's write-in-place media and inherently faster chip negates that. It's same with DDR. You can get per DIMM bandwidth figures by multiplying the width per IC times the speed(in MT/s) the IC is running at. No needing to saturate or anything like that.
A single NAND flash die isn't enough to keep one of the controller's channels busy, because flash takes many microseconds to complete a read or write command, and even longer for erase commands. By contrast, 3D XPoint memory is fast enough that there is little to no performance to be gained from overlapping commands to multiple dies on a single channel
Bandwidth is determined by the internal connections to the IC. The manufacturer determines how wide and how fast it can be. So if they want 16GB Optane to be having 1GB/s it can. Why it runs at such speed and how wide it is only the engineers at Intel knows.