New Zen microarchitecture details

[krumme]

Ahem. Base 3 ghz for a 32 core part no problem? If thats with hsw like integer ipc i think amd shareholders will sleep very well. Lol.
Edit what i am saying is pls be more realistic. Xeon 24 core part 8890 v4 is 2.2ghz.

 

[The Stilt]

Thank you I'm not sure what "extremely tiny delta" do you mean... 2.8/3.2 is the part in question, so 400 MHz delta is that small? True, parts like i7-6700 have 600 MHz delta, but 400 MHz is not that smaller than 600 MHz, it's not tiny compared to it With 6700K it's only 200 MHz, and 6800K is similarly 400 MHz.

A delta of 150MHz ("all core boost" vs. "maximum boost") is EXTREMELY tiny for 8C/16T CPU. The point being that if AMD can guarantee 2.8GHz base clocks when all cores are stressed, then obviously the "maximum boost" cannot be limited by the TDP. Maximum boost is available on AMD CPUs when a single core is stressed and obviously there is no way a single stressed core operating at > 3.2GHz can exhaust the TDP, when eight cores could not exhaust it at 2.8GHz - 3.05GHz.

IMO either the frequencies claimed by "AMD Polaris" ain't true, or the Fmax is limited by the manufacturing process or by the design itself.

 

[krumme]

If 32 cores is 180w isnt it more likely its process fmax then?

 

[krumme]

It actually seems to me they were a bit lucky here in an difficult process situation.
They wouldnt be able to touch Intel 4 core perf anyway even in a optimal situation and 8c on desktop is both kind of a bit to early and a relatively insignificant market.
So its just bad vs meh. Doesnt make a difference for profit. Not that it usually matters for amd. Lol.
That leaves server where the real profit is anyway. Here low power 8c and up to 32c 180w on low freq is what was needed for that arch anyway.

 

[krumme]

I could have used a quad core zen with a small apu in my new thinkpad instead of this boring skylake i5 stuff. Then i could play bf1 at low res and settings. Now i will have to play tf2. Lol. Thats not bad. Games for Intel 520 is really really cheap...

 

[DrMrLordX]

Ahem. Base 3 ghz for a 32 core part no problem? If thats with hsw like integer ipc i think amd shareholders will sleep very well. Lol.
Edit what i am saying is pls be more realistic. Xeon 24 core part 8890 v4 is 2.2ghz.

Yeah I get what you're saying, it's just that for an 8c part, it isn't at all impressive. It really depends on tdp targets and cooling. 3 GHz may not be a reality for their 32c part, and obviously the launch window for the 32c part is going to be later anyway. Or so I would expect, given the limited information we've gotten from AMD thus far.

It may be late enough that the 24 and 32c parts will be A1 stepping regardless of what happens with the AM4 stuff.

 

[FieryUP]

A delta of 150MHz ("all core boost" vs. "maximum boost") is EXTREMELY tiny for 8C/16T CPU. The point being that if AMD can guarantee 2.8GHz base clocks when all cores are stressed, then obviously the "maximum boost" cannot be limited by the TDP. Maximum boost is available on AMD CPUs when a single core is stressed and obviously there is no way a single stressed core operating at > 3.2GHz can exhaust the TDP, when eight cores could not exhaust it at 2.8GHz - 3.05GHz.

IMO either the frequencies claimed by "AMD Polaris" ain't true, or the Fmax is limited by the manufacturing process or by the design itself.

I still can't see a huge problem there. AFAIK i7-6800K is 1-core Turbo: 36x, all-core Turbo: 35x, base: 34x. Small steps there too. And due to obvious TDP constraints (95W vs. 140W) Summit Ridge may not be able to compete with the "biggest fishes" (6900K and 6950X) anyway. Truth be told, it would still need both a higher base clock and a higher Turbo clock to compete with anything out there. I hope AMD wouldn't pull another Kaveri there, ie. I hope they don't f* up the clocks in the first iteration on using a new manufacturing process...

 

[Phynaz]

All I'm saying is that Intel's current (and supposedly their best) solution is simply not suitable to scale up to 32 cores, while AMD's solution was designed to scale up to 32 cores.

Citation needed.

I really don't think you understand how a ring bus works.

You can brush up here
http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/4
http://www.anandtech.com/show/8423/intel-xeon-e5-version-3-up-to-18-haswell-ep-cores-/4

 

[Arachnotronic]

Citation needed.

I really don't think you understand how a ring bus works.

You can brush up here
http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/4
http://www.anandtech.com/show/8423/intel-xeon-e5-version-3-up-to-18-haswell-ep-cores-/4

I just can't understand the argument that a ring bus connecting cores all on the same die will be inferior to an MCM.

 

[The Stilt]

If 32 cores is 180w isnt it more likely its process fmax then?

Depends what kind of turbo does such chip have. If the maximum turbo on these would be the close the same as on 4C/16T or 8C/16T, then it is definitely a process limitation. If the clocks for 4C/8T & 8C/16T parts are true, then those 32C/64T chips are unlikely to have higher than < 1500MHz base frequency.

 

[FieryUP]

Citation needed.

I really don't think you understand how a ring bus works.

You can brush up here
http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/4
http://www.anandtech.com/show/8423/intel-xeon-e5-version-3-up-to-18-haswell-ep-cores-/4

Thank you But if the ring bus works so magnificiently, then how come there's no 32-core Intel server processor? With KNL Intel already pushed the TDP envelope out to 245 Watts. Surely they could fit 32 cores in that TDP envelope, so what's stopping them? Maybe, just maybe there would be too many hops on those great rings. I don't want to convince anyone though, we have to wait and see what happens when both Naples and SKL-EP/EX hits the market and Anandtech can benchmark them head-to-head. I'm not saying Naples would win, but to me it seems like a smarter design (than the current BDW-EP/EX, not SKL-EP/EX) _if_ you target 32 cores. I'm also sure SKL-EP/EX will be able to scale up to 32 cores, maybe not at 14nm, but when it gets shrinked to 10nm with CNL-EP/EX.

 

[Phynaz]

Thank you But if the ring bus works so magnificiently, then how come there's no 32-core Intel server processor?

So you are saying that the reason why Intel doesn't make a 32 core CPU is because of the ring bus.

That's a hell of a stretch. Do you have anything to back up that statement?

 

[FieryUP]

So you are saying that the reason why Intel doesn't make a 32 core CPU is because of the ring bus.

That's a hell of a stretch. Do you have anything to back up that statement?

Nope. I only use pure logic, like a really-really stupid person You see, with KNL Intel dropped the ring bus architecture, and with SKL-EP they also develop a different solution. The current ring bus solution is over at BDW-EP/EX. With KNL you could say: yeah, but with 72 cores you obviously need something different. But then how come when adding only 4 additional cores (BDW-EX --> SKL-EP/EX) Intel still cannot re-use the BDW-EP/EX ring bus concept?

I would love to put my hands on a 24-core BDW-EX and hammer it with specific memory intensive workloads that scale up to a certain pre-defined number of cores. I'm pretty sure (but again, no proof, since I don't have such a system at hand) scaling wouldn't be stellar even with "only" 24 cores.

But I think it would be best to get back to Zen, and not deal with silly Intel matters

 

[inf64]

If AMD plans to launch sub 3Ghz 8C/16T Summit Ridge, even with Haswell like IPC, then I think it will be a failure, especially if those Turbo clocks are true.

It would mean that Zen is process limited frequency wise and this would imply that they cannot compete with i7 (and maybe even OCed i5 SKUs ). They absolutely need 3.2Ghz at the minimum with 3.7Ghz ST Turbo clocks to be even a viable option to enthusiasts (even those on the budget). Nobody would buy a Haswell 8C chip that cannot clock over 3.4Ghz while most likely blowing up the TDP at those clocks to ~250W range. IMO it would be a total disaster of a launch if AMD launches such SKU lineup.

They better delay the whole launch by one quarter, get the clocks where they need to be and launch with good quantities and super aggressive pricing to capture as much market as possible before intel rolls out another next gen product line.

 

[The Stilt]

If AMD plans to launch sub 3Ghz 8C/16T Summit Ridge, even with Haswell like IPC, then I think it will be a failure, especially if those Turbo clocks are true.

It would mean that Zen is process limited frequency wise and this would imply that they cannot compete with i7 (and maybe even OCed i5 SKUs ). They absolutely need 3.2Ghz at the minimum with 3.7Ghz ST Turbo clocks to be even a viable option to enthusiasts (even those on the budget). Nobody would buy a Haswell 8C chip that cannot clock over 3.4Ghz while most likely blowing up the TDP at those clocks to ~250W range. IMO it would be a total disaster of a launch if AMD launches such SKU lineup.

They better delay the whole launch by one quarter, get the clocks where they need to be and launch with good quantities and super aggressive pricing to capture as much market as possible before intel rolls out another next gen product line.

IMO since the process is what it is, Zeppelin won't ever be too appealing to the enthusiasts (no OC margin). I speculated a long ago that AMD likely needs to release Zeppelin clocked "balls to the wall" right out of the box just to be competitive.

The yields on 14nm LPP will most likely improve, however giving additional time for the process to mature doesn't change it's characteristics.

Unless AMD changes the manufacturing process to 16nm FF+ (which is obviously not going to happen for various reasons), I doubt they'll ever reach higher than 3.6GHz stock clocks. Besides, Zen appears to target rather low frequencies from the design side (similar to Hound-cores).

 

[superstition]

if the ring bus works so magnificiently, then how come there's no 32-core Intel server processor?

Probably a silly question but how similar is it to ATI's old ring buses for GPUs?

http://www.anandtech.com/show/2231/9
http://www.anandtech.com/show/1810/4

 

[looncraz]

It looks nice, but there's no ring in Naples

It was just an example - was also just a 16-core CPU, LOL! I think I was very tired when I made that...

 

[krumme]

Depends what kind of turbo does such chip have. If the maximum turbo on these would be the close the same as on 4C/16T or 8C/16T, then it is definitely a process limitation. If the clocks for 4C/8T & 8C/16T parts are true, then those 32C/64T chips are unlikely to have higher than < 1500MHz base frequency.

The 14nm 22 cores Intel e5 2699 is 2.2 base and turbo 3.6
http://ark.intel.com/m/products/91317/Intel-Xeon-Processor-E5-2699-v4-55M-Cache-2_20-GHz
The 18 cores 22nm haswell xeon is 2.3 base and 3.6 boost.
http://ark.intel.com/m/products/810...v3-45M-Cache-2_30-GHz#@product/specifications
Your argument does not make sense if i understand you correctly. I asume your argument can be applied to Intel as well but they dont boost to 4 ghz either.

As for the 1500 base, and writing this on a note 5 phone at 2.1, i am a pretty confident this high freq design compared to a a57 will be min 1900 for the 32c part. And thats under the assumption the "random guy drops by" numbers is right.

 

[looncraz]

IMO either the frequencies claimed by "AMD Polaris" ain't true, or the Fmax is limited by the manufacturing process or by the design itself.

I'm leaning more towards "AMD Polaris" not having accurate numbers... mostly because it would instantly be a worthless product if true...

If the numbers are right, Zen will be a dismal failure and will not outperform existing top Piledriver parts in single threaded applications. 3Ghz Zen is only worth ~4.5~4.8GHz Piledriver.

Single-threaded Zen turbo clocks must be ~4Ghz to be a worthwhile product in the consumer market.

If I can't get ~4Ghz Zen 8-core clocks with high-end air or half-decent water cooling then the product will not be worth my investment in next year's upgrade cycle.

If the clocks given are accurate, an eight-core Zen will need to cost about what an FX-8350 does today to be a value.

 

[krumme]

I just can't understand the argument that a ring bus connecting cores all on the same die will be inferior to an MCM.

We all know the old "not true quad core" argument.
The all important thing here is not what is best - and Intel solution probably is - but does it actually matter?
I mean if mcm and some seamicro 2.5d torus mixup is what is needed and its cheap to boot who cares if its not elegant or technically the most optimal?

 

[KTE]

Most big uarch changes need a few metal spins, definitely with a new process too. First two alone are just to iron out the bugs. Typically, B0 is where power and clocks start being dealt with. Agena didnt launch till the short lived B2, which was buggy till B3.

My opinion... AMD has a scenario of needing a high performing uarch now with good performance per watt. Clocks, while imperative, can be slowly dealt with in later revisions and processes. A stagnant uarch, ahem Bulldozer, can't, for years.

Sent from HTC 10
(Opinions are own)

 

[krumme]

Will you give it a rest guys. I understand your feelings that unfortunately Intels rip off in desktop consumer highend class will not stop. And it does sucks. But its hardly a revolution outside of a minority.

And certainly this kind of blaming amd is kind of childish if not even ironic when we all buy Intel 4/6 core stuff. Its just what it is.
We have consoles. Notebook. Servers. All far more important than desktop highend.
For ones amd actually makes a product that makes sense from a business perspective.

 

[The Stilt]

I'm leaning more towards "AMD Polaris" not having accurate numbers... mostly because it would instantly be a worthless product if true...

That's based on driver / bios EVV model data, the same code which calculates the correct default voltage for the ASIC, based on leakage.

Those value represent default voltage vs. frequency of a ASIC with medium leakage characteristic.

Shows pretty clearly the point where it starts going south. Ideally Ellesmere (Polaris 10) would not operate faster than ~1000MHz. I'd expect this was the frequency range originally (prior Pascal release) planned.

 

[Arachnotronic]

I'm leaning more towards "AMD Polaris" not having accurate numbers... mostly because it would instantly be a worthless product if true...

If the numbers are right, Zen will be a dismal failure and will not outperform existing top Piledriver parts in single threaded applications. 3Ghz Zen is only worth ~4.5~4.8GHz Piledriver.

Single-threaded Zen turbo clocks must be ~4Ghz to be a worthwhile product in the consumer market.

If I can't get ~4Ghz Zen 8-core clocks with high-end air or half-decent water cooling then the product will not be worth my investment in next year's upgrade cycle.

If the clocks given are accurate, an eight-core Zen will need to cost about what an FX-8350 does today to be a value.

Zen was clearly not designed for the consumer desktop CPU market, but for the server market. Power efficient cores and being able to pack a lot of them into a given area/power envelope is a key factor there.

Anyway, if AMD was able to sell those power hog FX chips to enthusiasts, they should be able to move much more power efficient Zen chips + a more modern platform into that same market.

It's unrealistic to think that AMD can after being so behind and being so R&D constrained just "decide" to come out with an architecture that's an "Intel killer" as some have hoped. That's never been a realistic expectation, IMHO.

 

[looncraz]

That's based on driver / bios EVV model data, the same code which calculates the correct default voltage for the ASIC, based on leakage.

Those value represent default voltage vs. frequency of a ASIC with medium leakage characteristic.

Shows pretty clearly the point where it starts going south. Ideally Ellesmere (Polaris 10) would not operate faster than ~1000MHz. I'd expect this was the frequency range originally (prior Pascal release) planned.

What I see is a definitive improvement over 28nm in both frequency and voltage requirements.

Fmax is a function of process and design. The process should be able to switch transistors plenty fast enough at low enough current to support 4Ghz clocks or better... with the proper design. If Zen is clock-rate limited, I think it's all down to the cache system limiting clocks - the same problem they had in the Phenom II era, IIRC.

Still, I doubt AMD would move forward with 14nm LPP if they thought it would result in such a low clocked CPU. Gaining ~50-60% performance while losing 40~50% of your clock speed is not a good trade.