Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

---------------------------------------------------------------------------------------------------------------------------------------------------


FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[Ajay]

https://twitter.com/x/status/1712936607429403017

Again it looks like N2 will not be that much more denser than N3B. The demo recently done for CFET used 48nm gate pitch which according to Raichu is same as N3E and slightly lower than N3B !!!

Well, of course. CFET is in an experimental phase. Wait - is N2 supposed to be CFET?? Base N2 doesn't look very good. It should be better when High NA EUV machines are in place - still, we are talking diminishing returns until some breakthrough is made.

 

[jpiniero]

Again it looks like N2 will not be that much more denser than N3B. The demo recently done for CFET used 48nm gate pitch which according to Raichu is same as N3E and slightly lower than N3B !!!

Yep. N2P does increase the density a bit further but not much.

 

[trivik12]

Basically it looks like SRAM is not going to shrink that much(if at all). So we are not going to see crazy increases in cache unless they go for some novel solution using 3D packaging. But I am curious how nanosheet xtors perform. We should hopefully see something from Samsung and Intel before TSMC N2.

 

[Ajay]

Yep. N2P does increase the density a bit further but not much.

I'm curious about electrostatics. Is there a TSMC estimate chart anywhere with that?

 

[Hitman928]

I'm curious about electrostatics. Is there a TSMC estimate chart anywhere with that?

Are you talking about ESD protection guidelines, electromigration, or breakdown voltages?

 

[Ajay]

Well, the best we'll get if V/F curves, xtor max switching frequency, voltages, power. Last time I saw I really detailed breakdown was when Intel 22nm FinFET came out.

 

[Doug S]

Well, of course. CFET is in an experimental phase. Wait - is N2 supposed to be CFET?? Base N2 doesn't look very good. It should be better when High NA EUV machines are in place - still, we are talking diminishing returns until some breakthrough is made.

No you're right N2 is not CFET it is GAA. It isn't clear if TSMC is being conservative with scaling for N2 since it is their first use of GAAFETs and there will be density increases in follow ons along with backside power, or if they feel they've hit some sort of scaling limit without getting back into the multipatterning business this time with EUV. We'll have to wait for the specs of N2P to find out I guess.

I agree that it is silly to worry about scaling with experimental use of CFETs. The goal would be to just have them working at all, worrying about density comes later when they are putting together a manufacturable node based on CFET, which probably doesn't happen until early next decade. I wasn't able to see the tweet, apparently it had been deleted.

 

[NostaSeronx]

AIST/Rapidus is in consortium with Canon for NIL for 2nm and lower.



NZ2C 2021 = 160 wph
NZ2C 2023 = 190 wph
NZ2C 2025 = 210 wph
Minimum production clusters is 6 of main tool: 315 wph is the bare minimum expected. 8 for example would be double NZ2C: 420 wph.

Defect density of NZ2C-2023 target is 0.001. Thus, Advanced NIL is logic ready in 2024.

Forgot, that NZ2C is pseudo-mass production ready do to its performance against EUV: https://global.canon/en/news/2023/20231013.html
NZ2C-current and 2025-update put it on-par with NXE3800(NZ2C-rel)/NXE4000(NZ2C-2025up). With the mask update it can also compete against EXE5000(NZ2C-rel w/ new mask) and EXE5200(NZ2C-25up w/ new mask)

 

[Doug S]

If Canon is saying this is mass production ready then where are the test ARM chips or SRAMs or ANYTHING made with it that can have its performance/specs/etc. characterized against TSMC or Samsung output?

 

[moinmoin]

Canon is not a foundry like TSMC, it's a tools manufacturer like ASML.

 

[Ajay]

AIST/Rapidus is in consortium with Canon for NIL for 2nm and lower.

View attachment 87228

NZ2C 2021 = 160 wph
NZ2C 2023 = 190 wph
NZ2C 2025 = 210 wph
Minimum production clusters is 6 of main tool: 315 wph is the bare minimum expected. 8 for example would be double NZ2C: 420 wph.

Defect density of NZ2C-2023 target is 0.001. Thus, Advanced NIL is logic ready in 2024.

Forgot, that NZ2C is pseudo-mass production ready do to its performance against EUV: https://global.canon/en/news/2023/20231013.html
NZ2C-current and 2025-update put it on-par with NXE3800(NZ2C-rel)/NXE4000(NZ2C-2025up). With the mask update it can also compete against EXE5000(NZ2C-rel w/ new mask) and EXE5200(NZ2C-25up w/ new mask)

Wow, I have no fricking idea how those kind of rates can be accomplished with a direct contact patterning system. Seems impossible (though maybe this is for much less complex dice, which would help). There's a reason we use the EM spectrum.

 

[NostaSeronx]

If Canon is saying this is mass production ready then where are the test ARM chips or SRAMs or ANYTHING made with it that can have its performance/specs/etc. characterized against TSMC or Samsung output?

This:

Canon is not a foundry like TSMC, it's a tools manufacturer like ASML.

To Doug:
However, it is more likely the first step would be BEOL improvements. With FEOL-components SRAMs, Gates, etc still being fabbed by 193i.

GF28A = 1x metal pitch for M1~M8, 2x metal pitch for M9.
7LP = 1x/~40nm metal pitch for M0~M3, 2x/~80nm metal pitch for M4~M9.
Intel 4 = 30~50 metal pitch for M0~M4, 60 metal pitch M5~M6, 84 metal pitch for M7~M8, etc.

GlobalFoundries can simple replace its 4 EUV tool spots with 8 NZ2C (yep, that small). Then, use that to get 12FDX's BEOL to have M1~M8 with 56nm. Thus, return to the more ideal T-beol for AI/High Density components.

The second step where they bleed into FEOL. For GlobalFoundries it would be getting flat/thin-FMG replacing round/tall-MIPS on FDSOI. Where the metal gate is basically as thin/tall as the Hi-K/SiO2, Hi-K/HfO2 layer.

Image edit example:
Canon NIL----------------------ASML 193i

Wow, I have no fricking idea how those kind of rates can be accomplished with a direct contact patterning system. Seems impossible (though maybe this is for much less complex dice, which would help). There's a reason we use the EM spectrum.

Low-loss and really fast print rate. The flash component can get up to 10000C.

Fill/fluid spread/resist spread time (jet component):
1.5s = 60wph ~ 2015
1.1s = 80wph ~ 2017
1.0s = 100wph ~ 2019

Less dense = faster fill rate. So, it is very important to note that this is probably with >40-nm metal pitch. Rather than <30-nm metal pitch. There is also a bunch of other total optimizations reducing time. So, I can't really use the fill time anymore. Since, they cut time everywhere.

Wait, I'll just do effective time.
0.75~0.8s = 160 wph ~ 2021
0.7s = 190 wph ~ 2023
0.65~0.7s = 210 wph ~ 2025

Yeah, it is probably with larger DRAM/Logic Cu-BEOL:

The showcase only shows 64nm and 48nm metal pitches for logic nodes. [I saw this before, which is why I hinted towards 12FDX]

Also finally found it again:

(That full wafer imprint: https://fuse.wikichip.org/news/3010...r-scale-engine-half-square-foot-silicon-chip/ )

Canon appears to want 4MFI(4x of SFI) to be the standard (May 2019):


This explains the wph increases more better. Increased imprint size => higher throughput. Opposite of EUV, where the mask shrinks NA -> High NA, NIL increases its mask size.

So, 2025 is 4MFI at 1.75s actual or 2MFI at 0.6s. Risk region seems to be improved by Canon over time. So, 190wph might be 2MFI at 0.75s.

GlobalFoundries if they buy NZ2C for Fab 8.1/8.2, Fab 1.3/1.4, Fab 7.H for 12FDX. Then, it is likely that they will choose 4MFI.

 

[Ajay]

GlobalFoundries can simple replace its 4 EUV tool spots with 8 NZ2C. Then, use that to get 12FDX's BEOL to have M1~M8 with 56nm. Thus, return to the more ideal T-beol for AI/High Density components.

Just out of curiosity, what is GFs next node after 12FDX?

 

[NostaSeronx]

Just out of curiosity, what is GFs next node after 12FDX?

No clue yet. It really depends on what 12FDX's Gate Length is... 20nm = 10FDX/9FDX, 14nm = 6FDX/3FDX

However, Europe Chips Act and North American Chips Act money requirements have them doing "10nm" = 64~68CPP and "7nm" = 45~48CPP.


28nm FDSOI <130CPP
14nm FDSOI 90CPP
10nm FDSOI 64CPP
7nm FDSOI 45CPP

CEA-Leti website back in 2016 had this for the design rules of 7nm FDSOI; it had that target because of IBM/GloFo's 7nm FinFET EUV: https://www.researchgate.net/public...ning_and_dual_strained_high_mobility_channels
It is also why Leti's 7nm FDSOI is built as closely to the above as possible:

"7 nm technology presented in this paper follows the aggressive historical scaling trend from earlier planar and FinFET technologies. The process flow, based on replacement metal gate (RMG) and Self-Aligned Contact (SAC)..."
RMG and SAC comes from the 7nm FinFET paper.
"A combination of ~1.6GPa tensile-strained NFET and ~1.6GPa compressively strained medium-Ge content PFET provides the desired drive currents."
Strained NFET and Strained Ge-content PFET also comes from that 7nm FinFET paper.

Leti's benchmark for this 7nm FDSOI had it around 50% faster than the 7nm FinFET shown above.

Which is why 12FDX's gate length in production is very important. As if it is shrunk from 22FDX/early 12FDX(2018~2019 version had 20Lg), it is likely doing the 65nm/45nm/32nm PDSOI thing. Where 65nm introduces the 35nm Gate Length, and they use it again for 45nm and 32nm. Except, it is 12FDX/6FDX/3FDX. If it is Lg ~15nm, then the minimum is a 3-nm market node.

With that 7nm FDSOI project, it is actually 3nm FDSOI in marketing. So, the minimum possible is 3FDX.

 

[Frenetic Pony]

If Canon is saying this is mass production ready then where are the test ARM chips or SRAMs or ANYTHING made with it that can have its performance/specs/etc. characterized against TSMC or Samsung output?

Nano imprint stuff is better for low layers of silicon, it has problems aligning one layer atop the other due to expansion/contraction etc. Thus this tech is super useful for silicon photonics, and is in experimental production for flash (SSDs/etc.) but remains questionable for "a whole lot of layers" like logic ends up with.

It'd be interesting to see if someone starts using it for low layer chiplets, such as AMD's SRAM stacking, but even there the layer count is still 13 or so (has it changed since the original run?).

If chiplets could somehow 3D stack such that you'd start slicing the layers up vertically then this might start being really useful. If you could do a vertical stack of say, backside power delivery/logic/interconnect and then successfully (both engineering and economics wise) stack one atop the other with some 3d packaging tech this might outcompete ASML handily. But considering 3d stacking is still in it's infancy and already constrained it doesn't seem likely anytime soon.

 

[Doug S]

Canon is not a foundry like TSMC, it's a tools manufacturer like ASML.

Sure but they have to have a way to test that this thing they've spent years developing actually works, so they either have a foundry partner they have been working with during development and/or they have a test fab. They are apparently making claims about stuff like defect rates that NostaSeronx has posted here, they only way you can get that data is to operate this equipment in some type of fab setting and actually produce working chips.

So why not release some information about the chips it has produced to compare them with equivalent chips produced via traditional photolithography?

Now it sounds like they would only be using this for some layers, but they could still compare chips produced with those layers using NIL vs traditional on stuff like performance (if there is any difference aside from defect rates) and more importantly cost - not only of hardware but power since to say EUV is power hungry is a major understatement lol

 

[NostaSeronx]

Sure but they have to have a way to test that this thing they've spent years developing actually works, so they either have a foundry partner they have been working with during development and/or they have a test fab. They are apparently making claims about stuff like defect rates that NostaSeronx has posted here, they only way you can get that data is to operate this equipment in some type of fab setting and actually produce working chips.

First test fab is Toshiba/Kioxia: https://global.canon/en/news/2017/20170720.html

AIST is the second fab:
[At present, 65nm CMOS line is in operation in the SCR, and the installation of 20 new equipment is in the pipeline already. Four technologies: fine lithography technology, nanosheet structure formation technology, gate stack formation technology, and nanosheet transistor integration technology will rise in the front-end project.

The installation of equipment in the line will start in Feb. to Mar. 2022 and the new equipment will start rolling in late 2022. Furthermore, nanosheet FET full process will become available in FY2025.]

They didn't even decide to rename the tool with all the upgrades installed.
"TOKYO, July 20, 2017—Canon Inc. announced today that the company has provided the FPA-1200NZ2C"
"On October 13, 2023, Canon announced today the launch of the FPA-1200NZ2C nanoimprint semiconductor manufacturing equipment"

Canon FPA-1100 NZ2 -> Canon's 1-cluster, first modern NIL tool // 2013-2015
Canon FPA-1200 NZ2C -> Canon's 4-cluster, second modern NIL tool // 2015+ => Toshiba/Kioxia tool
Technically, spec-wise this should be moved up to like FPA-1300 or something. // 2023+ => AIST tool

It has always been placed with Logic in mind in Canon's roadmaps.

Memory is smaller, while Logic is BOLDED from 2018.

The Japan NEDO/AIST thing going on from 2021 is also specifically for logic.
[By pressing nanometer-scale patterns onto substrates like a stamp to form minute circuits, Canon's technology holds the promise of huge cost reductions and energy savings. Nanoimprint lithography has received an environmental award* for its energy-saving technology in manufacturing ultrafine semiconductors, and is expected to be a technology that supports the IoT society. The equipment has reached the level of primary functionality required to mass-produce memory, and Canon is currently working with semiconductor device manufacturers to verify its operation for practical mass production. Meanwhile, the New Energy and Industrial Technology Development Organization (NEDO) of Japan has selected Canon's technology as part of a subsidized project for developing advanced logic manufacturing process applications.]

March 2023 AIST Cu-BEOL => No electrical properties different from standard 193i/d Cu-BEOL.

Logic=>


AIST 65nm (present) -> AIST 2nm (2025) -> Rapidus's second 2nm tool chain, other than the IBM EUV one.

However, I think we won't see anything for real till NIL is added to this:


Reason for them not launching the NZ2C earlier: It was never meant to be a mass production tool. Since 2015, they were hyping up the NZ3C, their next-generation >6-cluster/imprint stations tool.
Photomask Japan 2016: "NZ3C is also under development as the next generation machine, The overlay is <3.5nm at 200wph and the defect density is 0.01DD."

NZ2C current/2025 target, NIL Tool Fab(Utsunomiya Phase2?) finishes ramp: ~1.0nm overlay, 210 wph, 0.001DD, sub-2nm EPE metrics.

Canon Utsunomiya Office to install new manufacturing facilities, strengthen manufacturing capacity for semiconductor lithography systems | Canon Global

TOKYO, October 6, 2022—Canon Inc. announced today that the company will install new manufacturing facilities at its Utsunomiya Office, which produces semiconductor lithography systems and other devices. The new facilities are scheduled to commence operation in the first half of 2025.

global.canon

Edit: I have been looking through some NIL papers. The 210 wafer per hour seems to be SPECIFICALLY for 10-nm Half Pitch. While, there will be improvement for existing half-pitch shown with even more aggressive print speed.

1x-nm (20~38nm Mx) = 210 wph
2x-nm (40~58nm Mx) = 231 wph
3x-nm (60~78nm Mx) = 254 wph
4x-nm (80~98nm Mx) = 280 wph
This WPH scaling stops at 150nm Mx, but continues scaling at a slower rate to 2xxx-nm Mx.

However, I am not sure if they even noticed that they are improving fill time for older pitches. Also, they haven't updated the tool/install cost on us from SFIL days. So, who knows what the end cost will be. As I can't find out what FPA1200-NZ2C was ever sold as:


Current day:
193i = ~$90m to ~$120m
EUV = ~$150m to ~$270m

Guessing based on how weird Canon/MII marketed afterwards would basically have to be $40m to $60m. The cost of ownership parity against photolithography has been maintained. Canon's NIL being the cheapest for the 7nm BEOL all the way to the 3nm BEOL. Unlike EUV, only IBM is using EUV for Nanosheet fabrication, can possibly be more aggressively used for FEOL. However, the SFIL to JFIL rename and MII buy out basically killed FEOL side:

https://willson.cm.utexas.edu/Research/Sub_Files/SFIL/Publications/2003/SPIE%20MOSFET%20Paper%20Final.pdf

http://cnt.canon.com/wp-content/uploads/2014/11/EIPBN-2008-IBM-storage-class-memory.pdf

SFIL => Solutions out-of-sight, no idea when targets will be hit.
Current day JFIL/NZ2C => Solutions in-sight, within two years all FEOL/BEOL/MEMS/etc capability targets will be hit.

 

[igor_kavinski]

AMD CEO Su surprisingly leaves Cisco board of directors | igor´sLAB

Lisa Su, CEO of AMD, has reportedly left her position on the board of Cisco and Analog Devices. The reason for her resignation is not known, but it is believed to be related to AMD’s strategy toward…

www.igorslab.de

Big things coming for AMD now that it gets more of Lisa Su's time and attention?

 

[Ajay]

AMD CEO Su surprisingly leaves Cisco board of directors | igor´sLAB

Lisa Su, CEO of AMD, has reportedly left her position on the board of Cisco and Analog Devices. The reason for her resignation is not known, but it is believed to be related to AMD’s strategy toward…

www.igorslab.de

Big things coming for AMD now that it gets more of Lisa Su's time and attention?

Also AMD going into an area where they will compete with Cisco. In those circumstances, it's customary to step down.

 

[FlameTail]

Is there any information on the Samsung SF4 (4LPP) and SF4P (4LPP+) nodes regarding density, power and performance?

 

[Henry swagger]

TSMC Places Confidence In 3nm Node, Compares It To Intel 18A: Better Maturity, Cost & Delivery Time

TSMC believes that it will retain its process leadership over Intel's 18A node with its 3nm process owing to better maturity & cost.

wccftech.com

Tsmc felling the pressure? .. no chance they can beat 18A with power via with 3nm finfet 🤔💻

 

[Geddagod]

TSMC Places Confidence In 3nm Node, Compares It To Intel 18A: Better Maturity, Cost & Delivery Time

TSMC believes that it will retain its process leadership over Intel's 18A node with its 3nm process owing to better maturity & cost.

wccftech.com

Tsmc felling the pressure? .. no chance they can beat 18A with power via with 3nm finfet 🤔💻

No.

 

[lightisgood]

TSMC Places Confidence In 3nm Node, Compares It To Intel 18A: Better Maturity, Cost & Delivery Time

TSMC believes that it will retain its process leadership over Intel's 18A node with its 3nm process owing to better maturity & cost.

wccftech.com

Tsmc felling the pressure? .. no chance they can beat 18A with power via with 3nm finfet 🤔💻

TSMC implies that Intel 18A beats N3P in sphere of power, performance and density.
I think that N3P's real competitor is Intel 3, not 18A.

 

[DrMrLordX]

Tsmc felling the pressure? .. no chance they can beat 18A with power via with 3nm finfet 🤔💻

Yup it's hard to beat vaporware.

 

[Geddagod]

TSMC implies that Intel 18A beats N3P in sphere of power, performance and density.

I did not get that implication from reading that

I think that N3P's real competitor is Intel 3, not 18A.

I highly doubt Intel 3 is even going to be that competitive with TSMC N3...