Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[DrMrLordX]

Legit or load of hogwash?

Would need more info than that one story to confirm. That being said, if HiSilicon/Huawei has the (limited) ability to use their "14nm" process to produce performance similar to some N7 or slightly worse than uh hey good for them? You'd really need to put the SoC under an electron microscope to know more.

 

[FlameTail]

Samsung and TSMC Reportedly Struggling with 3 nm Yields

According to Korean business news publication ChosunBiz, both Samsung and TSMC are struggling with their 3 nm node yields. The two companies have different approaches to their 3 nm nodes, with Samsung using GAA FET (Gate All Around), whereas TSMC is continuing with its FinFET technology. That...

www.techpowerup.com

Samsung and TSMC yields still below 70% apparently

 

[Doug S]

Samsung and TSMC Reportedly Struggling with 3 nm Yields

According to Korean business news publication ChosunBiz, both Samsung and TSMC are struggling with their 3 nm node yields. The two companies have different approaches to their 3 nm nodes, with Samsung using GAA FET (Gate All Around), whereas TSMC is continuing with its FinFET technology. That...

www.techpowerup.com

Samsung and TSMC yields still below 70% apparently

Everyone knows N3B yields suck, what we're all curious about are N3E yields. I figure if they were really bad we probably would have heard rumors by now, like we did in the runup to N3. But if they were stupendous TSMC would produce another one of those graphs like did they showing N5 yields at the start of mass production outpacing N7 and N10 yields at the same time.

 

[lightisgood]

Everyone knows N3B yields suck, what we're all curious about are N3E yields. I figure if they were really bad we probably would have heard rumors by now, like we did in the runup to N3. But if they were stupendous TSMC would produce another one of those graphs like did they showing N5 yields at the start of mass production outpacing N7 and N10 yields at the same time.

And vice versa, if they were really GOOD we probably would have heard rumors by now. Right?

I think that N3E has to start by end of this year at least 60~65% yield point and enter HVM by mid'24 at 70~% yield.
Yes, this is the dead-line for iPhone 16.

 

[qmech]

CEO of research firm reveals what he says is the big secret behind the Kirin 9000S chipset

The CEO of a research firm tells the South China Morning Post that the Kirin 9000S was built on SMIC's 14nm node.

www.phonearena.com

Legit or load of hogwash?

We have fairly solid transistor densities from N+1 and N+2. Those numbers are significantly better than what one would expect from a 14nm process and right in line with the major 7nm processes.

The news making the rounds that the Kirin 9000S is "not a real 7nm chip" can be traced back to a single quote from an article in the South China Morning Post:

In an email interview, the chief executive at Tokyo-based electronics research firm Fomalhaut Techno Solutions, Minatake Mitchell Kashio, told the Post that he believes the Kirin 9000s CPU was made via SMIC’s 14-nm process based on their own handset teardown. He indicated that some special techniques were added to push the chip’s performance closer to a 7-nm grade processor. (SCMP)

I would not be at all surprised if these "special techniques" consisted mainly of a (high degree of) multiple patterning. Filtering this through a non-technical lens, as would be logical when a CEO gives a quote to a newspaper, and I could easily see that becoming "special techniques".

However, considering that SMIC has access to ASML scanners that are better than what TSMC introduced their N7 process on and optics at least on that scale as well, I don't see the need for SMIC to have done anything terribly different than what the other major players have done to reach 7nm. Certainly, one would want some better evidence than a vague "special techniques" claim.

 

[NostaSeronx]

This should be what is going on:

Primary Node​	Gen1 DTCO Node​	Gen2+ DTCO Node​
14SFE​	14SF+​	12SF+/SF++​
10SFE (Gen1 SAQP)​	8SFE (N+1)​	7 (N+2)​
7SFE (Gen2 SAQP)​	5 (N+3)​	3 (N+4)​

SMIC's 7 is really just an extremely optimized 10nm node. (Samsung 8nm :: 3P+2N :: uHD Cell, SMIC 7 :: 1P+1N :: HD Cell)

 

[Ajay]

And vice versa, if they were really GOOD we probably would have heard rumors by now. Right?

I think that N3E has to start by end of this year at least 60~65% yield point and enter HVM by mid'24 at 70~% yield.
Yes, this is the dead-line for iPhone 16.

Uh, that’s low. TSCM, Apple, et all will want something closer to 90% by the summer. If N3E is 70% that’s a lot of scrapped dice.

 

[lightisgood]

TSCM, Apple, et all will want something closer to 90% by the summer.

TSMC couldn't do that in this summer on N3B.
I don't have any positive info about N3E now.
Do you have it ?

 

[Doug S]

And vice versa, if they were really GOOD we probably would have heard rumors by now. Right?

I think that N3E has to start by end of this year at least 60~65% yield point and enter HVM by mid'24 at 70~% yield.
Yes, this is the dead-line for iPhone 16.

70% is terrible. TSMC has entered mass production over 80% for N5, N7, and N10, and were near 90% within a quarter or two. Apple would start serious talks with Intel if N3E yields are barely improved from N3B.

 

[Doug S]

We have fairly solid transistor densities from N+1 and N+2. Those numbers are significantly better than what one would expect from a 14nm process and right in line with the major 7nm processes.

The news making the rounds that the Kirin 9000S is "not a real 7nm chip" can be traced back to a single quote from an article in the South China Morning Post:



I would not be at all surprised if these "special techniques" consisted mainly of a (high degree of) multiple patterning. Filtering this through a non-technical lens, as would be logical when a CEO gives a quote to a newspaper, and I could easily see that becoming "special techniques".

However, considering that SMIC has access to ASML scanners that are better than what TSMC introduced their N7 process on and optics at least on that scale as well, I don't see the need for SMIC to have done anything terribly different than what the other major players have done to reach 7nm. Certainly, one would want some better evidence than a vague "special techniques" claim.

I agree. TSMC did N7 on DUV with high initial yields, and like you say SMIC has better DUV scanners than TSMC did. So even if they did "real" 7nm wouldn't be surprising. From what I understand those new DUV scanners are improved enough TSMC theoretically could produce N5 wafers (or something very close to it) using those instead of EUV.

Whether SMIC is doing 7nm or 14nm or something in between is irrelevant. You don't use processes because of the marketing feature size, you use it for the performance that results. So how the 9000S performs is what matters. Samsung is proof you can have a really nice marketing node name that produces chips with performance two generations behind the claimed node.

Sure the node size in terms of actual realized transistor density matters for cost per chip, but for China's goals that's less important than the performance piece. These leading edge (for China) chips will go in products that are less cost sensitive - high end smartphones are probably the most cost sensitive of the bunch, with stuff like server CPUs, AI chips, and military applications other reasons they want this capability and those markets aren't going to care too much if the chips are 2 or 3 times more expensive than TSMC chips would be for equivalent performance.

 

[FlameTail]

If 70% yield is considered terrible... what words can describe Samsung's 20-35% yields for their 4nm node last year?

 

[Ajay]

TSMC couldn't do that in this summer on N3B.
I don't have any positive info about N3E now.
Do you have it ?

N3B, as has been discussed, was really a failed process node for TSMC. There is no factual info on N3E yet, that I'm aware of. Since TSMC isn't bragging, the assumption is that it's not ramping as well as N7 & N5 did. It's possible that TSMC's whole N3 line could be borked - we'll just have to see. I'm sure their process engineers are doing double shifts to work this stuff out.

 

[Frenetic Pony]

N3B, as has been discussed, was really a failed process node for TSMC. There is no factual info on N3E yet, that I'm aware of. Since TSMC isn't bragging, the assumption is that it's not ramping as well as N7 & N5 did. It's possible that TSMC's whole N3 line could be borked - we'll just have to see. I'm sure their process engineers are doing double shifts to work this stuff out.

N3E has been widely discussed by TSMC, including I do believe higher yields than N3B as part of the entire reason for making it, though I don't think they've revealed any actual yield numbers from their early runs. At the very least they've announced cutting EUV layers and double patterning, and you'd expect that to increase yields.

Edit: rumors for now: https://www.tweaktown.com/news/8494...ood-production-is-starting-earlier/index.html

 

[Doug S]

N3E has been widely discussed by TSMC, including I do believe higher yields than N3B as part of the entire reason for making it, though I don't think they've revealed any actual yield numbers from their early runs. At the very least they've announced cutting EUV layers and double patterning, and you'd expect that to increase yields.

Edit: rumors for now: https://www.tweaktown.com/news/8494...ood-production-is-starting-earlier/index.html

That article is 18 months old.

 

[hemedans]

I agree. Heck, I would like the Samsung 4nm to succeed, but I'm not very optimistic about its prospects. Even with the relatively new X3 core, the Tensor G3 doesn't seem to be much different from the G2 in performance. I just hope that Samsung can demonstrate some improvement in efficiency.

SD 4 Gen 2 is doing fine so is Exynos 1380, 1330 and Sd 7s gen 2, Atleast now we know 4LPP is better than Tsmc 6nm in efficiency.

 

[FlameTail]

SD 4 Gen 2 is doing fine so is Exynos 1380, 1330 and Sd 7s gen 2, Atleast now we know 4LPP is better than Tsmc 6nm in efficiency.

How do you conclude that?

1380, 1330, 4G2, 7sG2 all are made on 4LPE or 4LPX I believe. The Tensor G3 is the first chip to be made on 4LPP

 

[FlameTail]

https://x.com/Tech_Reve/status/1709859249738985831?s=20

Samsung is reportedly accelerating the development of 2nm

 

[H433x0n]

https://x.com/Tech_Reve/status/1709859249738985831?s=20

Samsung is reportedly accelerating the development of 2nm

Samsung's node descriptions are meaningless. I feel like Korean publications just have an annual tradition of taking TSMC's latest node and announcing they're working on the n-1 process so clueless tech press will write about it. Meanwhile they haven't done anything of note since like 2018-2019.

 

[hemedans]

How do you conclude that?

1380, 1330, 4G2, 7sG2 all are made on 4LPE or 4LPX I believe. The Tensor G3 is the first chip to be made on 4LPP

Anandtech assume it's 4LPP (due to timing of release) so is other sites like Notebookcheck. Compare to last year E1280, soc released these year are much better.

 

[FlameTail]

Anandtech assume it's 4LPP (due to timing of release) so is other sites like Notebookcheck. Compare to last year E1280, soc released these year are much better.

Anandtech may be mistaken.

I have seen more sources say otherwise.

 

[FlameTail]

How do you conclude that?

1380, 1330, 4G2, 7sG2 all are made on 4LPE or 4LPX I believe. The Tensor G3 is the first chip to be made on 4LPP

CORRECTION:

E1380 and E1330 are made on 5LPE.

4G2, 7sG2 are reportedly made on 4LPX

 

[hemedans]

CORRECTION:

E1380 and E1330 are made on 5LPE.

4G2, 7sG2 are reportedly made on 4LPX

Can you show me source for that?

 

[jpiniero]

70% is terrible. TSMC has entered mass production over 80% for N5, N7, and N10, and were near 90% within a quarter or two. Apple would start serious talks with Intel if N3E yields are barely improved from N3B.

You can only imagine how bad Intel's yields are. There's a reason why Intel is only using designs which are extremely cuttable.

Although... there was talk back during 10 nm that part of the reason that Intel took the strategy they took... was because they thought if they got stuck, everyone else would. They were wrong of course but perhaps TSMC is getting there. N2's going to be a tough sell.

 

[Doug S]

https://x.com/Tech_Reve/status/1709859249738985831?s=20

Samsung is reportedly accelerating the development of 2nm

I might as well announce I'm accelerating the development of my backyard rocket that will take me to the Moon as I have equal odds of making that happen as Samsung does of releasing something that's close to what TSMC will call N2 and Intel will call 20A at production worthy yields.

 

[trivik12]

https://twitter.com/x/status/1712936607429403017

Again it looks like N2 will not be that much more denser than N3B. The demo recently done for CFET used 48nm gate pitch which according to Raichu is same as N3E and slightly lower than N3B !!!