Discussion Intel Nova Lake in H2-2026: Discussion Threads

[Khato]

The other notable advantage for Intel on the server side are their accelerators. Those result in Intel still being the default choice for certain applications. Being friendly with/less of a threat to NVIDIA also helps Intel get something out of the current AI spending spree at least. Just have to hope that they can figure out the issues with Foveros Direct such that CWF and DMR aren't literally DOA.

Back to NVL, 2x bLLC is indeed still a POR configuration - who knows what 'roadmap' those denying such have seen. Two other recent additions are of far greater interest though. Definitely fun to see Intel start to make proper use of their modular tile design to bring more variations to market.

 

[511]

The other notable advantage for Intel on the server side are their accelerators. Those result in Intel still being the default choice for certain applications. Being friendly with/less of a threat to NVIDIA also helps Intel get something out of the current AI spending spree at least. Just have to hope that they can figure out the issues with Foveros Direct such that CWF and DMR aren't literally DOA.

Clearwater forest from the projection shared by Intel will be decent enough but DMR needs to hit it out of the park

 

[Geddagod]

Clearwater forest from the projection shared by Intel will be decent enough but DMR needs to hit it out of the park

It looks like it's around Turin Dense specint2017. It's hard to call that decent when its coming so much later and only like half a year before Venice, and without AVX-512.
Also, something interesting:

Turin Dense: 12 x 86mm2 N3 dies, 1x 423mm2 IOD
Clearwater Forest: 12 x 55mm2 18A dies, 3 x 350mm2 Intel 3 dies ( C&C server games.keep.loading), 2 x 240mm2 IOD

Some really simple and rounded math, using a die cost calculator
Turin Dense: 12 x 28.9 + 1 x 134 = $481
Clearwater Forest: 12 x 17.5 + 3 x 108 = $534
And Intel 7 tile cost, and more expensive hybrid bonding cost, is not included in this. I also used a 0.1 defect density for both N3 and N5, and realistically it should be better for both nodes by now.

So Turin has ~60% more leading edge silicon, but less than half the N5 class silicon, and then also doesn't use any N7 silicon.... realistically assuming all node costs are equal between TSMC and Intel (I doubt TSMC is more expensive tbh but whatever) Turin should be a more cost efficient design as well.

 

[adroc_thurston]

Intel is dead in data centre right?

Yeah.

Not really in every metric GNR is the 2nd best server CPU after Turin but it has lot's of stuff that AMD doesn't have like More PCI-E Memory Bandwidth advantage they are shipping every GNR they make and DMR is another big upgrade like Venice Dense is over Turin Dense it will arrive later than Venice Dense.

Man you need to slow down and lay off the speeds.
GNR doesn't really have any on-paper advantage relative to Turin and gets brutalized in workload perf.
Venice does even scarier things to DMR.

 

[511]

It looks like it's around Turin Dense specint2017. It's hard to call that decent when its coming so much later and only like half a year before Venice, and without AVX-512.
Also, something interesting:

Turin Dense: 12 x 86mm2 N3 dies, 1x 423mm2 IOD
Clearwater Forest: 12 x 55mm2 18A dies, 3 x 350mm2 Intel 3 dies ( C&C server games.keep.loading), 2 x 240mm2 IOD

Some really simple and rounded math, using a die cost calculator
Turin Dense: 12 x 28.9 + 1 x 134 = $481
Clearwater Forest: 12 x 17.5 + 3 x 108 = $534
And Intel 7 tile cost, and more expensive hybrid bonding cost, is not included in this. I also used a 0.1 defect density for both N3 and N5, and realistically it should be better for both nodes by now.

So Turin has ~60% more leading edge silicon, but less than half the N5 class silicon, and then also doesn't use any N7 silicon.... realistically assuming all node costs are equal between TSMC and Intel (I doubt TSMC is more expensive tbh but whatever) Turin should be a more cost efficient design as well.

Intel also gets the wafer margin as well for the dies AMD Doesn't

 

[511]

GNR doesn't really have any on-paper advantage relative to Turin and gets brutalized in workload perf.

it has read the spec sheet first before saying this Turin doesn't have highest mem bandiwdth and it kicks Turin in many workloads

 

[adroc_thurston]

it has read the spec sheet first before saying this Turin doesn't have highest mem bandiwdth

Only with MCRDIMMs which are pure esoterica.

and it kicks Turin in many workloads

Okay lay off the crackpipe.

 

[Thunder 57]

You’re jumping around all over the place. The discussion was about whether there will be 288 MB bLLC variants of NVL-S.

There wont be. Just like I don't believe the duzl 3DV cache 9950X. Despite his "trust me bro" record on many things I agree on this.

 

[inquiss]

Only with MCRDIMMs which are pure esoterica.

Exactly. Completely changes the cost equation to the point that it's well, pointless.

 

[Fjodor2001]

There wont be. Just like I don't believe the duzl 3DV cache 9950X. Despite his "trust me bro" record on many things I agree on this.

Well, there are lots of opinions. I'm more interested in the reasoning behind it than just a statement that there will or will not be such variants.

So in your case, why do you think there won't be any 2xbLLC for NVL-S (and similarly not any 2x X3D for zen6)? It's been speculated about for quite some time, so it shouldn't be totally unrealistic that there eventually could be such variants too after all.

 

[Khato]

Clearwater forest from the projection shared by Intel will be decent enough but DMR needs to hit it out of the park

Agreed, Intel's problem on both CWF and DMR is not performance.

 

[Thunder 57]

Well, there are lots of opinions. I'm more interested in the reasoning behind it than just a statement that there will or will not be such variants.

So in your case, why do you think there won't be any 2xbLLC for NVL-S (and similarly not any 2x X3D for zen6)? It's been speculated about for quite some time, so it shouldn't be totally unrealistic that there eventually could be such variants too after all.

Fair enough. Cost as has been mantioned and it would be a very niche market. Cross CCD/tile latency would limit usefulness. Areas that could benefit like VM's would likely want more PCIe, more memory, or both.

So I'll rephrase; I don't THINK there will be either. I would be pleasantly surprised if there were if for no other reason to compare them to their since Vcache/bLLC models.

 

[Joe NYC]

You think AMD's FAD goals are conservative then? If AMD has the goods to lead in client they should chip away at that share? Data centre is just working away at the old dinosaur contracts bites at a time.

When AMD has a superior product, AMD gains share, if the product is ~ similar to Intel, then Intel can maintain even a lopsided market share advantage.

That's how it has worked until now, but AMD is making some inroads with the OEMs, even if miniscule. So that alone can result in a slight market hare shift.

But a real solid shift will only happen when AMD releases a clearly superior mobile CPU / SoC vs Intel.

 

[Joe NYC]

Only with MCRDIMMs which are pure esoterica.

Which is not compatible with JEDEC, AFAIK.

Is anyone really buying MCRDIMM or are these uses purely for benchmarks? Especially with real MRDIMM on the horizon, which, I presume, DMR will be using.

 

[Geddagod]

Intel also gets the wafer margin as well for the dies AMD Doesn't

True, but do you also think 18A yields are near N3 yields?
I didn't add the Intel 7 IO tile costs as well, and Intel has told us that Intel 7 wafer cost is absurdly expensive. There's a bunch of really expensive packaging as well.
All things considered, even with margin stacking, I would be shocked if CLF is less expensive for Intel to manufacture than Turin is for AMD.

TBH, I think if CLF performs only as well as Turin Dense, it would be really disappointing. It honestly also doesn't make that much sense it couldn't perform decently better, but both the 8:1 fleet reduction math vs the 8280, and the 2.13x more perf than 144C SRF (who knows what workload this is though), line up at the same estimate.

The implications this has on Darkmont perf/watt is terrible. A 192 core chip should not be tying a 288 core chip, even if it has SMT. Unless that extra 50 watts of TDP Turin Dense has vs CLF is really putting in that much work lol.

 

[Geddagod]

When AMD has a superior product, AMD gains share, if the product is ~ similar to Intel, then Intel can maintain even a lopsided market share advantage.

That's how it has worked until now, but AMD is making some inroads with the OEMs, even if miniscule. So that alone can result in a slight market hare shift.

But a real solid shift will only happen when AMD releases a clearly superior mobile CPU / SoC vs Intel.

Might be why its rumored Intel went ahead and is using N2 for the 4+8 tile too instead of 18A-P.
The risk of losing laptop market share might be too great.
Really interested in seeing how this stacks up against N3 Zen 6 mobile.

 

[Joe NYC]

Might be why its rumored Intel went ahead and is using N2 for the 4+8 tile too instead of 18A-P.
The risk of losing laptop market share might be too great.
Really interested in seeing how this stacks up against N3 Zen 6 mobile.

That is a big setback for Intel 18A, that of the 4 die configurations, only 1 is Intel 18A.

OTOH, Intel is going full steam 18A on Panther Lake. Which is something I find hard to reconcile.

One way to reconcile it is that Intel bet big on 18A some time ago, when PTL design was frozen, and then, it came back under delivering, especially on clocks speeds that are needed to be competitive on desktop. So decision was to bet on TSMC N2. (Some say MJH made this bet). But notebook bound 4+0+4 is still 18A...

We are getting a trickle of PTL numbers coming out, but really nothing on Medusa 1 die and its competitiveness, so hard to make any conclusions.

At this time, 2 years ago, Strix Point looked quite solid on AMD side, but ended up under delivering (while Kracken is flying under the radar as far as OEM acceptance).

There are 2 big changes with Medusa 1:
- N3P makes it more competitive vs. node used by Intel (vs to Strix)
- LP cores make up the 2nd big deficit AMD had (vs competition)

It's something but not enough to know the competitive landscape a year from now.

 

[adroc_thurston]

Agreed, Intel's problem on both CWF and DMR is not performance.

Hahahhahaahhahaha hahahahaha holy shi-YES THEY ARE. Yes they are.

while Kracken is flying under the radar as far as OEM acceptance

doing good.

There are 2 big changes with Medusa 1:
- N3P makes it more competitive vs. node used by Intel (vs to Strix)
- LP cores make up the 2nd big deficit AMD had (vs competition)

It's also z6.
MDS1 also offers the CCD config if you're into speed racing.

 

[511]

True, but do you also think 18A yields are near N3 yields?

The dies are 55mm2 for Clearwater forest so yields shouldn't be a problem

All things considered, even with margin stacking, I would be shocked if CLF is less expensive for Intel to manufacture than Turin is for AMD.

It is possible that it is cheaper to produce than if we count margin stacking

TBH, I think if CLF performs only as well as Turin Dense, it would be really disappointing. It honestly also doesn't make that much sense it couldn't perform decently better, but both the 8:1 fleet reduction math vs the 8280, and the 2.13x more perf than 144C SRF (who knows what workload this is though), line up at the same estimate.

Intel usually base it on SPEC In server like AMD does
You can always check Intel.com/performanceindex

The implications this has on Darkmont perf/watt is terrible. A 192 core chip should not be tying a 288 core chip, even if it has SMT. Unless that extra 50 watts of TDP Turin Dense has vs CLF is really putting in that much work lol.

Depends on workload tbh and benchmark not out yet and I feel like Intel also botched the L3 on Clearwater Forest hence the issue(based on Years of Intel Botching L3 in Client and Server) the fabric for sure is bad only 35 GB/s.

Might be why its rumored Intel went ahead and is using N2 for the 4+8 tile too instead of 18A-P.
The risk of losing laptop market share might be too great.
Really interested in seeing how this stacks up against N3 Zen 6 mobile.

I doubt performance is only the reason cause they have cut Capex for next year.

 

[DavidC1]

One way to reconcile it is that Intel bet big on 18A some time ago, when PTL design was frozen, and then, it came back under delivering, especially on clocks speeds that are needed to be competitive on desktop. So decision was to bet on TSMC N2. (Some say MJH made this bet). But notebook bound 4+0+4 is still 18A...

So the terribleness of Intel foundry results now are going to be way worse with Novalake generation, unless Nvidia uses Intel substantially.

Depends on workload tbh and benchmark not out yet and I feel like Intel also botched the L3 on Clearwater Forest hence the issue(based on Years of Intel Botching L3 in Client and Server) the fabric for sure is bad only 35 GB/s.

Yea that must be how the performance goes from 32% in Skymont to 17% in Clearwater Forest.

Intel's problem is not just the core. The entire outfit is underperforming.

 

[poke01]

I can see nova lake-S being very good for jellyfin and handbrake

 

[511]

I can see nova lake-S being very good for jellyfin and handbrake

WCL is enough for that the volume product for this kind of stuff

 

[Fjodor2001]

WCL is enough for that the volume product for this kind of stuff

WCL? It’s abbreviation overload when searching for that, and I assume you don’t mean World Cricket League.

 

[DrMrLordX]

I can see nova lake-S being very good for jellyfin and handbrake

Why handbrake?

 

[poke01]

Why handbrake?

CPU encoding. Loves lots of cores. WCL is okay but Nova Lake has more cores.