Discussion Intel Nova Lake in H2-2026: Discussion Threads

[Khato]

AMD claims 5% extra die space and gets ~ 40% in DC from SMT. Intel's implementation appears to be both fatter, and less capable.

Of course they claim that. You always want to claim that a feature you have and your competition doesn't is super duper awesome. Doesn't mean it's reality. Out of curiosity, happen to know of any reviews that have tested server workloads on Epyc with SMT on/off? I only did a quick search, so plausible that there are some which I missed.

All that SMT does is allow the core to have two threads active such that the core's execution resources can be better utilized. As such, you could intentionally code a program such that SMT would yield 2x the performance. Outside of such contrived scenarios though, how much benefit SMT provides depends on how well a given workload can utilize the core's execution resources. If a single thread can fully load the core then SMT reduces overall performance. Whereas in the far more common case where there are free resources, then the other thread can make use of those and provide a 10-30% overall performance gain.

With the mess which Intel's P core is, I can easily see removal of SMT being a net win for both client and server. Whereas SMT on the upcoming converged core may show more benefit for a smaller area penalty and hence make sense again for server. Realistically it may end up being the case that Intel's converged core will have both ST and SMT variants, with client using ST only and server having both ST and SMT products for their appropriate markets.

 

[dangerman1337]

It's coming back with Coral Rapids though in 2028-29 xDd customer must be complaining that we get the Same vCPU count even though the performance is doubled

If it's coming back to Coral Rapids will that mean TTL/HML will have it with their iterations of Unified Core?

 

[adroc_thurston]

You always want to claim that a feature you have and your competition doesn't is super duper awesome

You know well enough this statement is silly given Intel's been using SMT for far longer.

Doesn't mean it's reality.

You also know well enough that SMT area costs are minimal.
The price you pay is validation complexity.

With the mess which Intel's P core is, I can easily see removal of SMT being a net win for both client and server.

It's a net loss for perf and a net win for Intel's perpetually incompetent post-Si validation teams.

 

[Khato]

You know well enough this statement is silly given Intel's been using SMT for far longer.

Intel is saying that on their P-core design, SMT cost them 15% area and increased single thread performance per watt by 5%. Meanwhile AMD is saying that SMT only costs them 5% and increases multi-threaded performance by 20-40%. Each is putting their respective spin on their design decisions. Not sure how pointing that out qualifies as 'silly'.

You also know well enough that SMT area costs are minimal.
The price you pay is validation complexity.

The claim of +15% area for Intel's P-core isn't minimal. I suspect they arrived at that figure by including both the bare minimum duplicated structures required (probably close to the 5% AMD claims) and the many other minor design tweaks/bug fixes they've added over the years specific to SMT.

 

[OneEng2]

I don't recall where I got the 40% (it wasn't AMD's claim), but here is 33%:

https://phoronix.com/benchmark/result/intel-xeon-6369p-vs-amd-epyc-4345p-smt-benchmarks/geometric-mean-of-all-test-results-result-composite-ix6vae4sb.svgz

This one also shows how little Intel gets from SMT.

 

[adroc_thurston]

Not sure how pointing that out qualifies as 'silly'.

Point being it's a featured Intel had and will have.

The claim of +15% area for Intel's P-core isn't minimal.

I don't think it actually is 15%.
Even SMT4 on Marvell Triton had low single digit overhead.

and the many other minor design tweaks/bug fixes they've added over the years specific to SMT.

You don't need anything like that.

 

[coercitiv]

Each is putting their respective spin on their design decisions.

FYI in the meantime Intel recanted:

we are reintroducing simultaneous multi-threading (SMT). Moving away from SMT put us at a competitive disadvantage. Bringing it back will help us close performance gaps.

 

[Covfefe]

FYI in the meantime Intel recanted:

Moving away from SMT put us at a competitive disadvantage.

That particular part of that quote doesn't make sense. Intel only dropped hyperthreading on Arrow Lake and Lunar Lake. The lack of SMT is pretty low on the list of issues with those CPUs. Server is where SMT matters the most, and they haven't dropped it for any server products. That reads to me as Lip Bu Tan trying to distance himself from his predecessor.

 

[adroc_thurston]

and they haven't dropped it for any server products.

They did.
For DMR. It's a disaster.

 

[Covfefe]

They did.
For DMR. It's a disaster.

Not out yet.

 

[adroc_thurston]

Not out yet.

Yeah but they talked it all in context of the server roadmap.

 

[jpiniero]

Really I wouldn't expect Intel to be competitive in server again until they commit to TSMC.

 

[adroc_thurston]

Really I wouldn't expect Intel to be competitive in server again until they commit to TSMC.

Process node is the least of their problems in server.

 

[Covfefe]

Yeah but they talked it all in context of the server roadmap.

He said they're bringing back SMT with Granite Rapids, which is already out.

 

[Darkmont]

He said they're bringing back SMT with Granite Rapids, which is already out.

What? They took out SMT with LNC and now PNC, the point is that LBT saw DMR without SMT and knew it immensely hurt their competitiveness with Venice. Nothing in the letter even implies that Granite Rapids is the generation bringing back SMT. Why would the CEO announce bringing back a feature to DCAI products that hasn’t even left the segment yet, and launched before his tenure?

 

[LightningZ71]

Getting back to the design and circuit costs/benefit of SMT, we need to keep in mind that AMD and Intel have used quite different strategies in their approach to implementing it. Intel tends to prefer to share as many resources as possible in their implementation, reducing the XTOR cost, but also taking a bit of a performance hit in the process. AMD has tended to statically partition and duplicate structures instead of sharing them, resulting in a few more XTORs being spent, but also saving on some of the XTORS that are involved in sharing and deconflicting resources. These decisions will affect the gains from each implementation.

AMD's choice is largely an artifact of their cores being server first for the last few generations and may not carry forward.

 

[MS_AT]

AMD has tended to statically partition and duplicate structures instead of sharing them, resulting in a few more XTORs being spent, but also saving on some of the XTORS that are involved in sharing and deconflicting resources.

Could you link your source for the breakdown what is statically partitioned, what is watermarked and what is shared for HT? In AMD case that information is in software optimization guide among other sources. Is that true for Intel too?

 

[511]

https://twitter.com/x/status/1962193853924233314

 

[Khato]

I don't recall where I got the 40% (it wasn't AMD's claim), but here is 33%:

https://phoronix.com/benchmark/result/intel-xeon-6369p-vs-amd-epyc-4345p-smt-benchmarks/geometric-mean-of-all-test-results-result-composite-ix6vae4sb.svgz

This one also shows how little Intel gets from SMT.

Thanks, though despite being run on server hardware only a portion of the Phoronix benchmark suite translates to server workloads. Still, good to have some independent objective data in the conversation.

 

[Khato]

That reads to me as Lip Bu Tan trying to distance himself from his predecessor.

Yup, distance himself from his predecessor by overruling the engineers. We all know how well it worked out for Intel the last time they had a CEO who thought he knew more than the engineers... That was BK passing on EUV lithography for 10nm.

 

[511]

Yup, distance himself from his predecessor by overruling the engineers. We all know how well it worked out for Intel the last time they had a CEO who thought he knew more than the engineers... That was BK passing on EUV lithography for 10nm.

Well He has made some very good cuts as well which are getting Overlooked he has cut many Program Engineers/Marketing and he has killed coaches as well not to mention PPT makers

 

[coercitiv]

Yup, distance himself from his predecessor by overruling the engineers.

He's much more likely to make this type of decision based on (updated) reports from engineering teams. You need to keep in mind the information LBT received may not necessarily be the same as Pat. (due to changes in company environment and structure, updates in simulations etc.)

 

[511]

He's much more likely to make this type of decision based on (updated) reports from engineering teams. You need to keep in mind the information LBT received may not necessarily be the same as Pat. (due to changes in company environment and structure, updates in simulations etc.)

He simply said if he hears complain from a customer it's not good for you at least he is making people accountable look at RPL Fiasco no one got their ass handed to them.

 

[regen1]

Yup, distance himself from his predecessor by overruling the engineers. We all know how well it worked out for Intel the last time they had a CEO who thought he knew more than the engineers... That was BK passing on EUV lithography for 10nm.

Well He has made some very good cuts as well which are getting Overlooked he has cut many Program Engineers/Marketing and he has killed coaches as well not to mention PPT makers

Well, it's not just the lay-offs are being done in a bad way but the talent bleed that has followed is on another level. Most that has been
done for talent attraction and retention is some lip-service.
Management is still very opaque with regards to its Silicon Photonics division. CEO meanwhile is still on Board of rival Silicon Photonics companies.
DMR's PCIe validation team has got similar treatment to what BK gave to SPR's validation team.
There were rumors last year that Intel's CCG head was going to get Raja treatment and laid off but instead the CEO got forced off and CCG head got promoted to interim CEO and then Product CEO.

 

[511]

Management is still very opaque with regards to its Silicon Photonics division. CEO meanwhile is still on Board of rival Silicon Photonics companies.

He has been on their board for years as for Intel's SiPho it's part of DCAI.

There were rumors last year that Intel's CCG head was going to get Raja treatment and laid off but instead the CEO got forced off and CCG head got promoted to interim CEO and then Product CEO.

I honestly don't like Intel Product CEO at all she sucks big time need a good head of products who knows the products.

DMR's PCIe validation team has got similar treatment to what BK gave to SPR's validation team.

As long as the work is doable by few people additional people doesn't make it fast but I don't have hope on Intel's management to make right decision Lip Bu can only do so much he needs to hold the management accountable.

Well, it's not just the lay-offs are being done in a bad way but the talent bleed that has followed is on another level. Most that has been

Every layoffs bleeds talent