This is incorrect for Zen5. Zen5 have whole front-end statically partitioned, it has decoders, op-cache and so on duplicated for each thread. They use significant amount of silicon just for smt which ain't used fot 1t at all.
AMD says SMT is 5% of the die... so it's a pretty good use of space IMO.
Anyone still doubting that 52C on DT will happen?
What about all the talk on this forum from some people saying that no company will release such a CPU on the consumer market? They'll have to buy expensive HEDT / server / whatever if they want it. Too low mem bandwidth to feed the threads, no use cases for it, bla bla.
I certainly don't doubt (and never have) that Intel intends to release it. In fact, it has been my contention that Intel is going to market the crap out of it. Core count in the age of the Arrow Lake class architecture will be the equivalent of MHz in the age of Netburst.
Back in the day, AMD simply moved to model numbers that were created to show equivalent P4 clock speeds the AMD chip was performance equal to.
Not sure how one does such a thing with cores. Perhaps there is a general performance model number and a "Cine-performance" model number

.
You still doubt it’ll be released, or you admit your arguments against that happening were overruled by Intel (and AMD who will be releasing a similar 48/50T Zen6 CPU on DT)?
To be clear, AMD is releasing a 24c/48t Zen 6 on the desktop. I think there is word of LPE cores built into the IOD on the laptop processor (replacement for Strix Halo). If such a laptop processor was created, it would technically have 26c/52t if it had 2x12c CCD's connected with an IOD that contained 2 LPE Zen 6.
... and I am also of the opinion that this is a solution in search of a problem.
For people who actually utilize the kinds of programs that CB is designed to benchmark for, they will shell out the $$ for a Thread ripper that not only has lots more cores, but also has lots more bandwidth that these real world programs rely on.
Just my opinion though.