adroc_thurston
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- Jul 2, 2023
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there are so many stops xDd but even than it's horrendous they should make better L3
adroc_thurston
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Speculation for Nova Lake has that they are reducing their ring size to 8 compute stops by making the P cores pair up to share the L3. With 4 P cores pairs and 4 e core quads, they should be able to return to at least relative Coffee Lake R L3 performance, which was considered fairly good for it's day. What we don't know is how bad the base L3 cache lookup latency will be. Indexing L3 cache that large isn't something we've seen Intel do before. One one hand, they shouldn't have to face the latency that X3D cache hits going to a whole different die, but on the other hand, Intel's cache latency on their existing L3 caches isn't stellar to begin with.
adroc_thurston
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The last good one was Comet Lake even LNL L3 performance is bad it's roughly ~55 Cycles for 4 Cores
I wonder, will they advertise it as L3? Then they could boast big latency advantage over Zen
[then they could get rid of L1.5 marketing, or whatever they are calling this current naming abomination]I don't care tbh all I care is the latency figure their L3 has been horrible past few gensI wonder, will they advertise it as L3? Then they could boast big latency advantage over Zen
I don't think it matters what they'll advertise it as. What matters is how it'll perform.I wonder, will they advertise it as L3? Then they could boast big latency advantage over Zen
The main question w.r.t. fat last level caches is this:
Will Intel NVL-S with BLLC be able to compete with Zen6X3D, primarily in gaming.
So far based on the comment in this thread, this is still an unknown.
Just wonder what will happen to Zen ThreadRipper (TR) once Intel NVL-S 52C is released.
Will AMD kill off the entire TR segment/lineup, since the perf/$ will render it pointless compared to NVL-S? Or will they keep only the top TR SKUs with 64-96C? But then it will perhaps be better to only keep the EPYC lineup for those that need perf above the much cheaper Intel NVL-S, and kill off TR.
Will AMD kill off the entire TR segment/lineup, since the perf/$ will render it pointless compared to NVL-S? Or will they keep only the top TR SKUs with 64-96C? But then it will perhaps be better to only keep the EPYC lineup for those that need perf above the much cheaper Intel NVL-S, and kill off TR.
Elfear
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Your use case of high-thread count and low mem bandwidth is rather niche and doesn't correlate with most folks who need MOAR cores.
He knows this but is trying to instigate? Not really sure the motivation there.
Indeed. But they right now use L0, L1, L2, L3 caches. More sane would be L1, L2, L3 (shared between the pair) L4 (LLC)
You keep bringing up this subject over and over again. Let's wait until the release — we'll find out then. I'm not interested in rehashing the same arguments again.
Well, apparently Intel thinks memory bandwidth with NVL-S will be sufficient for 52C. They'll also increase supported DDR5 speed on NVL-S. And w.r.t. PCI-E lanes , that'll also be increased on NVL-S.
But sure, there may be some corner use cases where more memory bandwidth or PCI-E lanes will be useful even on 52/64C, which could warrant TR. But it'll likely be few cases. So those needing that could be referred to EPYC SKUs instead, and TR could be killed off.
See my previous post.
If you're not interested, then you don't have to follow the discussion. Just like with all other sub-topics of NVL-S that we are discussing / speculating about in this thread.
Or perhaps you do not like the expected outcome of NVL-S for TR, so you'd rather like that discussion to be silenced even for those that are interested in it.
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I give Intel a little bit of slack for TGL-H as it was a mobile-only architecture. I expect a bit more latency there.
Threadripper is for real productivity, not Cinebench, lulz.
Oh this SKU is for real productivity as well E cores are not a meme like they used to be it should match a threadripper easily
So what new argument do you bring to the table? It's the same discussion as before. You think that majority of people buy TR for core spam (especially the 16 core model...) and so 52c Nova Lake part will displace that market.
You ignore the PCIe lane count adventage. And if the 52c part will launch as mainstream part then there is no way Intel will put 70 PCIe lanes on normal ATX mainstream board.
You ignore the MemBW advantage, you need to 12800MT/s to match quad channel 6400MT/s TR.
So the only market NovaLake 52c can grab is people needing relatively low memBW and Mem capacity per core with consumer PCIe requirements. The problem is we do not have data how big this market is and if it is already not dominated by 9950x or 285HX that.
So that is why I don't think 52 NovaLake will shake up the market in which TR operates.
It might be nice for those enthusiasts who feel TR was too expensive to begin with, but they anyway would not buy TR so it's hard to say TR lost sales to them.
So well that's it.
With this I agree. I should learn to better recognize and ignore fruitless discussions instead of participating in them.
Nice strawman piece. I never said I ignored the PCIe or memory bandwidth difference between TR and NVL-S. There are workloads where it may be useful. But as many others also have pointed out before, it's not an issue for a lot of MT workloads for the core and thread counts we're talking about (~50C/T).
Also, note that both PCIe lanes and memory bandwidth will increase with NVL-S.
What has changed is that it's quite clear now that we'll get 52C Intel NVL-S on DT based on information that has been published lately, despite that some people said it would not happen for the reasons you mentioned in your post above.
So in short: Intel disagrees with you.
I did. To repeat myself, I don't think Intel will give NVL-S 48 PCIe5 lanes + additional PCIe lanes via chipset. That would make the mobos too expensive for the consumer line. About memory BW, as I said you need to have 12800MT/s DC to match 6400MT/s QC. Mind you for TR since you are using 1 DPC you can easily reach full speed having 256GB even if DRAM is more expensive. I doubt Nova will let you use 12800MT/S fully populated as that would require 2 DPC.
For Z890 you have:
Max. overclocking frequency:
• 1DPC 1R Max speed up to 9200+ MT/s
• 1DPC 2R Max speed up to 7200+ MT/s
• 2DPC 1R Max speed up to 6400+ MT/s
• 2DPC 2R Max speed up to 5600+ MT/s
and I expect similar trend if higher values for Nova.
Intel or you? All I am saying is that Nova Lake will not invalidate TR as a product line. If Arrow Lake and Granite Ridge did not invalidate low core count TR setups, then I see no evidence hybrid Nova Lake will invalidate higher core count TR, where each core is the same. But that's it for me. Time will tell, might be you will be right but until new leaks come out I don't see new data that could be discussed. So I will see myself out.
There's another relevant issue and difference between what we know about NVL and CURRENT TR platforms, cache locality.
While we have no real idea about how well the two core die on NVL will talk to each other, we don't currently see much of a bandwidth handicap between the existing ARL core die and the IOD. If Intel makes any progress on L3 performance, and if they bring up the bandwidth between the core die and the IOD to keep up with higher supported ram speeds, we should hopefully see reasonable latency between distant cores. This will give NVL just two cache domains with 24 cores each to deal with. AMD currently has to handle four 6-core CCDs in that same space. For a full fat 48/52 core NVL, using 12 core Zen6 CCDs. That's at least 4 cache domains. If you use cut down 8 core chips and assume that 32 Zen 6 cores with SMT are equivalent to 48/52 NVL mixed cores, while that may seem like a lot of L3 with 4 pools of 48MB, it's still 4 different domains.
Depending on what that system is doing, that could be a big deal.
While we have no real idea about how well the two core die on NVL will talk to each other, we don't currently see much of a bandwidth handicap between the existing ARL core die and the IOD. If Intel makes any progress on L3 performance, and if they bring up the bandwidth between the core die and the IOD to keep up with higher supported ram speeds, we should hopefully see reasonable latency between distant cores. This will give NVL just two cache domains with 24 cores each to deal with. AMD currently has to handle four 6-core CCDs in that same space. For a full fat 48/52 core NVL, using 12 core Zen6 CCDs. That's at least 4 cache domains. If you use cut down 8 core chips and assume that 32 Zen 6 cores with SMT are equivalent to 48/52 NVL mixed cores, while that may seem like a lot of L3 with 4 pools of 48MB, it's still 4 different domains.
Depending on what that system is doing, that could be a big deal.
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