Fjodor2001
Diamond Member
- Feb 6, 2010
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Latest I've seen is that NVL-S will have 32 PCIe 5.0 lanes and 16 PCIe 4.0 lanes. Source:I don't think Intel will give NVL-S 48 PCIe5 lanes + additional PCIe lanes via chipset. That would make the mobos too expensive for the consumer line.
Are you saying that'll not be sufficient for most MT workloads on ~50C/T? What are you expecting them to be used for?
Yes, agreed. But who says you need all that memory bandwidth for most MT use cases on 52C/T?About memory BW, as I said you need to have 12800MT/s DC to match 6400MT/s QC.
Also, there are other aspects to consider, like the memory controller, caches, etc.
Intel, since they are the ones releasing it. So it means they think there is a market for NVL-S 52C on DT, with the memory bandwidth and PCIe lane config it has.Intel or you? All I am saying is that Nova Lake will not invalidate TR as a product line.
It will not invalidate all TR SKUs, but several of them. There'll be many MT workloads which will be handled much cheaper using NVL-S than TR.
Regarding the low core count TR SKUs, it must be a real niche market. E.g. someone that needs a lot of RAM but little CPU perf? But as long as they have the TR range anyway, I guess they might as well include them in it.
For those TR SKUs which still will be relevant after NVL-S (e.g. due to need for 64C+, or more total RAM), could EPYC SKUs not be used instead? Then they'd only need to maintain one combined HEDT/Server CPU range and platform.
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