Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[poke01]

Run SIMD code on Apple vs AMD and you will find it gets beaten in both power and perf/wattthe gap is not that big

Not bad for such an INT/FP focused CPU.

Math fun

The 9950X is just better here for peak performance. Now if Apple ever includes proper SVE2.1 then we can talk about DC talk. But have to say not bad especially the M4 Max with NEON it put up a good fight.

A Brief Study of Memory Bound Application Performance on M3 Ultra and M4 Max in Julia

Hello everybody! I wanted to share my Linear Algebra performance findings in Julia on the M4 Max and M3 Ultra in double precision floating point. As a Julia novice, I was hugely impressed how easy it was for me to brainstorm ideas in Julia and run quick performance tests. I subsequently sanity...

discourse.julialang.org

 

[poke01]

View attachment 134984
Not bad for such an INT/FP focused CPU.

View attachment 134985Math fun

The 9950X is just better here for peak performance. Now if Apple ever includes proper SVE2.1 then we can talk about DC talk. But have to say not bad especially the M4 Max with NEON it put up a good fight.

A Brief Study of Memory Bound Application Performance on M3 Ultra and M4 Max in Julia

Hello everybody! I wanted to share my Linear Algebra performance findings in Julia on the M4 Max and M3 Ultra in double precision floating point. As a Julia novice, I was hugely impressed how easy it was for me to brainstorm ideas in Julia and run quick performance tests. I subsequently sanity...

discourse.julialang.org

Now we stop saying Apple cores are better in everything. They are tailor made for extracting ST perf and for compiling your code but NEON is just too slow for SIMD tasks.

Now unless Apple changes direction or mandated by ARM, you won’t ever see SVE2 in their cores

 

[Thunder 57]

Now we stop saying Apple cores are better in everything. They are tailor made for extracting ST perf and for compiling your code but NEON is just too slow for SIMD tasks.

Now unless Apple changes direction or mandated by ARM, you won’t ever see SVE2 in their cores

I'm surprised no one has mentioned the massive L1 caches in particular for the Apple cores. Of course that is excellent for ST performance.

Oh and BTW, there is a thread for x86 vs ARM. Why can't these posts be there instead? Seems OT.

 

[aa887]

◾ “WilCat Lake” is going to be a ENORMOUS DISAPPOINTMENT in the range of chips under 10W (for possible fanless use).
➖ On the one hand, the “Qualcomm Snapdragon 8 Elite Gen 5” with an estimated TDP of 8W and an NPU with 80 TOPS, ideal for “Windows 11 Copilot Plus.”
➖ On the other hand, the AMD “Krackan Point” with a configurable TDP of 9W and an NPU of 50 TOPS, which exceeds 40 TOPS and is compatible with “Copilot Plus.”
➖ And finally, the “Intel WildCat Lake” with an estimated TDP of “less than 10W” and an NPU of 18 TOPS, INSUFFICIENT for “Copilot Plus.”
➖ I think Intel should implement its latest “NPU 6” design in “WilCat Lake” NOW, so that it can at least compete with an NPU that will be compatible with “Copilot Plus.”

 

[Magio]

◾ “WilCat Lake” is going to be a ENORMOUS DISAPPOINTMENT in the range of chips under 10W (for possible fanless use).
➖ On the one hand, the “Qualcomm Snapdragon 8 Elite Gen 5” with an estimated TDP of 8W and an NPU with 80 TOPS, ideal for “Windows 11 Copilot Plus.”
➖ On the other hand, the AMD “Krackan Point” with a configurable TDP of 9W and an NPU of 50 TOPS, which exceeds 40 TOPS and is compatible with “Copilot Plus.”
➖ And finally, the “Intel WildCat Lake” with an estimated TDP of “less than 10W” and an NPU of 18 TOPS, INSUFFICIENT for “Copilot Plus.”
➖ I think Intel should implement its latest “NPU 6” design in “WilCat Lake” NOW, so that it can at least compete with an NPU that will be compatible with “Copilot Plus.”

I don't know which part of this I find more comical, using NPU TOPS as the barometer on which to judge a chip, citing the max theoretical TOPS in conjunction with the lowest possible TDPs, acting like anyone in the world cares about "Copilot + PC" branding when everything actual people do with AI relies on cloud compute or suggesting Intel swap NPU6 into WCL now as if that's how chip design works.

... Or maybe it's the idea that the fanless Windows laptop market will be a significant segment within WCL's lifespan.

 

[dullard]

...

Please don't repost the same exact block of text in multiple threads. https://forums.anandtech.com/threads/intel’s-unified-core-there-is-hope.2630962/post-41545096

1) You misspelled Wildcat multiple times.
2) Qualcomm products don't really run x86 code well. For example, last I saw was only 90% compatibility in new games--let alone the hundreds of thousands of older games it can't play. https://overclock3d.net/news/gpu-di...ame-compatibility-with-its-new-adreno-x2-gpu/
3) You misspelled Krakan.
4) You don't need to put everything in quotation marks.
5) The rumors for Wildcat Lake is 40 TOPS total which is just enough for Copilot+.
6) Who is exactly going to be disappointed? Wildcat Lake is for the ultra low-end price computer tasks. These people aren't really the ones clamoring for Copilot+.

 

[aa887]

Please don't repost the same exact block of text in multiple threads. https://forums.anandtech.com/threads/intel’s-unified-core-there-is-hope.2630962/post-41545096

1) You misspelled Wildcat multiple times.
2) Qualcomm products don't really run x86 code well. For example, last I saw was only 90% compatibility in new games--let alone the hundreds of thousands of older games it can't play. https://overclock3d.net/news/gpu-di...ame-compatibility-with-its-new-adreno-x2-gpu/
3) You misspelled Krakan.
4) You don't need to put everything in quotation marks.
5) The rumors for Wildcat Lake is 40 TOPS total which is just enough for Copilot+.
6) Who is exactly going to be disappointed? Wildcat Lake is for the ultra low-end price computer tasks. These people aren't really the ones clamoring for Copilot+.

>> 5) The rumors for Wildcat Lake is 40 TOPS total which is just enough for Copilot+.
I don't think so. Copilot PC requires 40 TOPS ONLY IN THE NPU.