Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

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Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

Intel Alder Lake - NIntel Wildcat LakeIntel Lunar LakeMediatek D9500
Launch DateQ1-2023Q2-2026 ?Q3-2024Q3-2025
ModelIntel N300?Core Ultra 7 268VDimensity 9500 5G
Dies2221
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6TSMC N3P
CPU8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-coresC1 1+3+4
Threads8688
Max Clock3.8 GHz?5 GHz
L3 Cache6 MB?12 MB
TDP7 WFanless ?17 WFanless
Memory64-bit LPDDR5-480064-bit LPDDR5-6800 ?128-bit LPDDR5X-853364-bit LPDDR5X-10667
Size16 GB?32 GB24 GB ?
Bandwidth~ 55 GB/s136 GB/s85.6 GB/s
GPUUHD GraphicsArc 140VG1 Ultra
EU / Xe32 EU2 Xe8 Xe12
Max Clock1.25 GHz2 GHz
NPUNA18 TOPS48 TOPS100 TOPS ?






PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Joe NYC

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Thats a silly excuse. DC, HEDT, and mobile/laptop dont have to be mutually exclusive. Intel is still making more revenue on client / laptops than AMD is as an entire company.


Intel client computing: $7.9B
View attachment 131973

AMD entire company: $7.7B
View attachment 131974

Not for much longer. AMD Q3 revenue is estimated to be between $8 and $9 billion.
Q4 expectation > $9 billion
 

Meteor Late

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Dec 15, 2023
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At the end of the day, the reason for the low clocks is not that relevant, because TSMC could also have even higher clocks if not for lower yields in higher clocking parts. So with 18A you may say "oh the process is capable of higher clocks, it's just that yields would be terrible if it clocked at 5.4GHz", but then so could other TSMC parts like HX 370, could maybe hit 5.4GHz with those same terrible yields.
 
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Fjodor2001

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You're still getting decent LP cluster residency even during web browsing.
It's 4 cores at Raptor Cove performance running at 3.7GHz for Lunarlake. My desktop is a Cometlake Celeron(Skylake class) running at 4GHz, 2C/4T. It's more than fine.
Also, worst case the P cores (and iGPU) could be used to render the web page (which requires more performance), then when just reading the web page the LPE cores would be sufficient. The latter is what most time is spent on normally.
 

dullard

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May 21, 2001
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At the end of the day, the reason for the low clocks is not that relevant, because TSMC could also have even higher clocks if not for lower yields in higher clocking parts. So with 18A you may say "oh the process is capable of higher clocks, it's just that yields would be terrible if it clocked at 5.4GHz", but then so could other TSMC parts like HX 370, could maybe hit 5.4GHz with those same terrible yields.
There are two effects and your post seems like you are ignoring one of them.

1) Yes, you can set different targets (like frequency). But that parameter will impact yields (parametric yield). You could insist that a chip be 200 MHz faster, and you might get some that do perform that way, but there will be very few chips that hit your high target and you'll have to sell a lot of lower performing chips at a lower price.

2) But another very important reason for high or low clocks is the node design rules themselves. You can design cells with wide traces and/or more traces (less electrical resistance), widely spaced apart (less heat concentration), and hit high frequencies. Or you can design cells with narrow traces and / or fewer traces (more electrical resistance), spaced closely together (concentrated hot spots), and hit a high cell density. These are two completely different optimizations for the same manufacturing equipment.

An example from ARM chips is below. In the same die area (which means the same ultimate cost to the manufacturer), you could have 6 high performance cells (high frequency) or 9 cells (high density but low frequency). The 6 cells can clock at a significantly higher frequency. But, the 9 cells lets you use a smaller total area and thus smaller price tag.
1760450754631.png

If the reason for lower clocks is #1, then you are correct. All companies can ramp up clock frequencies, to a limit, if they are willing to have low yields. But, if the reason for lower clocks is #2, then that is a massive design difference that takes millions of dollars and many months of time to change. In this case, the reason for the low clocks is extremely relevant.

Right now we are talking about Intel's 18A node. But next year, they plan to have 18A-P ready which gives designers a range of widths, giving the chip designers a wide range of voltages to choose from, which impacts power, which impacts frequency.
 
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511

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Right now we are talking about Intel's 18A node. But next year, they plan to have 18A-P ready which gives designers a range of widths, giving the chip designers a wide range of voltages to choose from, which impacts power, which impacts frequency.
The biggest user would be intel products and this is design compatible with 18A
 

OneEng2

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Sep 19, 2022
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Also, that will be amortized over at least next 5-7 years, which Intel can easily handle.
... and in 5-7 years pay another 20bn for 14A or High NA?

It is an impossible situation for Intel to pay the same amount for development of new nodes as TSMC, and amortize the cost over a fraction of the chips.

As for "easily handle", that hasn't been the case. Something major would need to change.
At the end of the day, the reason for the low clocks is not that relevant, because TSMC could also have even higher clocks if not for lower yields in higher clocking parts. So with 18A you may say "oh the process is capable of higher clocks, it's just that yields would be terrible if it clocked at 5.4GHz", but then so could other TSMC parts like HX 370, could maybe hit 5.4GHz with those same terrible yields.
I think the point you are making is that sacrificing yields to meet clock targets is a losing proposition.

I agree.

At the end of the day, if you can't make money, you can't keep doing it.
 

Joe NYC

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Jun 26, 2021
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Or the parametric yields could be trash. Which is what insiders have been saying about 18a and neatly lines up with the relatively-low clockspeed for their top i9 SKU.

It will be interesting to see how Panther Lake does vs. competition. Most of the comments around here (and on Twitter) is about how Panther Lake does in vacuum. Discussing future CPU (Panther Lake) forgetting there will be future CPUs from competitors.

Medusa will likely ship within 1-2 quarters of Panther Lake, and Panther Lake will compete against Medusa for majority of its life.

As far as top performance and efficiency (vs. last gen from the same company).

Panther Lake:
+ new core
+ new iteration of SOC
= equivalent process node
= equivalent LP cores
- losing MoP advantage

Zen 6 Medusa:
+ new core
+ new iteration of SOC
+ better node
+ new LP cores

My conclusion is that Medusa will offer greater improvement over Strix than Panther Lake over Lunar Lake.
 

adroc_thurston

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Joe NYC

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Medusa is more a NVL competitor.

First release of Medusa is aiming at exactly the same mainstream mobile market as Panther Lake.

This first release of Medusa will have LPDDR5, RDNA3.5 and will be on N3P. So it can be released ahead of the rest of the Zen 6 line up.

I think subsequent releases of Medusa - Premium and Halo will compete with Nova Lake. Those versions of Medusa will have RDNA5 and LPDDR6

Keep in mind that AMDs mobile lineup is Asus exclusive for the first couple of months and hard to buy, it's not comparable to Intels mobile ramp.

Strix Point was a strange CPU and a strange launch - by being a premium chip and sold at high price. Medusa point will aim squarely at the mainstream mobile and will use the same socket.

Panther Lake ramp will not be instant. Higher volume is only expected in Q1 2026. Medusa Point will likely be announced around Mid 2026. So like I said, probably 1-2 quarter lag behind Panther Lake.

According to this roadmap Medusa Point is coming in 2027 by the way


Medusa Point is most likely mid 2026, Medusa Premium and Halo in 2027

I don't know whose roadmap that is...
 

Joe NYC

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It's a KRK1 replacement, you had KRK1 on the market everywhere soonafter launch.

It was probably a mistake on part of AMD to lead with Strix Point, while KRK1 has a lot better market positioning, with high degree of overlap with Lunar Lake, upcoming Panther Lake. MDS1 aims at the same segment.
 

Joe NYC

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it has like zero overlap with LNL.
KRK1 is a part for $800 laptops.
LNL is >$1200.

It seems like LNL is dropping fast to the lower price range. It is not much different from Kraken. First Lunar Lake laptop hit on Amazon search is Acer at $603 discounted from $899

 

Josh128

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Its very likely that MI450 and Venice will be the first AMD products out of the 2nm production line. OpenAI and Oracle are waiting, desktop and mobile users unfortunately will take a back seat to that.

AMD just confirmed MI450 Helios racks (which include Venice) are coming Q3 next year. This almost certainly means everything else is coming after. Q4 '26 or later.

1760479100053.png

 
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adroc_thurston

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It seems like LNL is dropping fast to the lower price range. It is not much different from Kraken. First Lunar Lake laptop hit on Amazon search is Acer at $603 discounted from $899
yeah but that's because Intel decided to nuke their ASPs.
Its very likely that MI450 and Venice will be the first AMD products out of the 2nm production line. OpenAI and Oracle are waiting, desktop and mobile users unfortunately will take a back seat to that.
what stops AMD from launching stuff at all once on N2p?
AMD just confirmed MI450 Helios racks (which include Venice) are coming Q3 next year. This almost certainly means everything else is coming after. Q4 '26 or later.
why lol
 

Joe NYC

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yeah but that's because Intel decided to nuke their ASPs.

Nuking ASPs to this extent, that a CPU that is intended for $1200 laptop is now selling in $600 laptop is not going to work out so well for margins.

It seems that Intel is trying to hold as much market as possible before Panther Lake launches, but what then, when MDS1 launches and will have costs similar to KRK1?

If you read comments on Twitter, all Intel fans are taking it as a given that ASPs go up. Which again, is talking about future Intel CPU, and disregarding the fact that the competitors will also launch their future CPUs.