Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[poke01]

This slide sums Intels Panther Lake claims up nicely. They managed to surpass MT on Lunar Lake by a significant margin-- thats pretty impressive as that showcases 18A node superiority vs N3B.

Now, they didnt specify if the +50% at the same power is the 8 core PTL vs 8 core LNL or 16 PTL core vs 8 core LNL, but I assume its the latter. If so its less impressive, but still a decent showing for 18A. And all this without on package memory of LNL.

By the way, what the heck is an IPU??

View attachment 131740

Image processing unit. Intel has very good ones

 

[poke01]

Okay now that I read about the Xe3 GPU, it’s actually a big upgrade. So many little things that make up for a great experience.

 

[Hulk]

Tech Report says Cougar Cove has a 256KB L1. I guess the L0 is gone or we don't get the details just yet. Lion Cove has 48+192=240 (L0+L1).

Also, just to be clear, slides are comparing power of TSMC N3B to 18A?

 

[CouncilorIrissa]

Tech Report says Cougar Cove has a 256KB L1. I guess the L0 is gone or we don't get the details just yet. Lion Cove has 48+192=240 (L0+L1).

Also, just to be clear, slides are comparing power of TSMC N3B to 18A?

That's just misreporting. The caching setup is unchanged (well, L1i capacity is missing, but they'd probably mention the change)

 

[511]

Means nothing without numbers on the axes.

I already leaked the number axis and fyi my graph used the same compiler as intel😛

 

[Doug S]

When you think about it, Intel needs cutting edge technology to only achieve 5.1GHz, that is incredibly depressive lol

Why are you so fixated on clock rates, especially for a mobile CPU? If Apple manages "only" 5.1 GHz for M6 on N2, will that be a failure of TSMC's technology?

You can throw stones at it if its performance underwhelms, but fixating on irrelevant details like clock rate is stupid.

 

[511]

When you think about it, Intel needs cutting edge technology to only achieve 5.1GHz, that is incredibly depressive lol

By that point both AMD/Intel newer are embarrassment cause Intel 7 can do 6.0ghz on much wider core than GLC.

 

[adroc_thurston]

cause Intel 7 can do 6.0ghz on much wider core than GLC.

?

 

[511]

?

I meant to say methodology of measuring.node by fmax is kind of bad otherwise Zen 4/5 would be embarrassment as RPL hits 6.0Ghz clock speed on I7.

 

[adroc_thurston]

as RPL hits 6.0Ghz clock speed on I7.

It 'hits' that as in explodes to bits, and in any case it's a bespoke handmade design.
PTL and Zens are normal things made with normal EDA tools and foundry PDKs.

 

[511]

It 'hits' that as in explodes to bits, and in any case it's a bespoke handmade design.
PTL and Zens are normal things made with normal EDA tools and foundry PDKs.

Doesn't change my point the comparison is not good for Fmax and Node perf both are different depending on the design/libs.

 

[DavidC1]

(2) It also shows that Panther Lake can't operate well with any more power than Lunar Lake. It reaches an asymptote in performance with increasing power. Thus, Panther Lake would not make a good desktop chip.

This is a mobile chip though. They have different curves, more optimized for lower leakage versus frequencies. A desktop optimized part would look different. Arrowlake-H's curve isn't significantly more fit for desktop either.

13% single thread gain over predecessor's best is not too shabby. Since apparently the same SoC can be targetted where Lunarlake fits as well. Having a wide dynamic range sacrifices optimization to do so.

Now, they didnt specify if the +50% at the same power is the 8 core PTL vs 8 core LNL or 16 PTL core vs 8 core LNL, but I assume its the latter. If so its less impressive, but still a decent showing for 18A. And all this without on package memory of LNL.

It isn't a true 16 core, since 4 of them are LPE. It's going from 4+0+4 to 4+8+4.

I laughed, but to be fair I don't think the x axis is zero indexed.

As you labeled it, Panther lake would have >50% lower power at the same performance level, but Intel only advertised >40%.

The MT chart fits with their numbers though. I don't know why the ST one is off, but it's also off significantly depending on whether you compare against Lunarlake or Arrowlake.

 

[DavidC1]

That annotation has the P core's L2 swapped (on outer edges) from the location where Intel's graphic puts it (inner edge along L2 cache). Probably won't make much difference on the size, but the annotation starting off wrong does not bode well for using the annotation as rough estimates of size.

The block diagram shot is showing 3.1x between P and E cores, pretty much same ratio as predecessor. We'll need an actual, accurate die shot to settle this but I don't think it'll change too much.

@Saylick P cores has to have IPC gains, because it clocks lower at 5.1GHz vs 5.4GHz on Arrow.

Intel gave no numbers on the performance improvement iso-clock from Lion Cove to Cougar Cove nor Skymont to Darkmont...

We know Pantherlake clocks lower at 5.1GHz versus 5.4GHz on Arrowlake-H. And being ~6% faster, along with rather significant changes for a Tick, it's not entirely unreasonable either. In fact, if it does work, I might call this "proper Lion Cove" that should have got 15-20% rather than 10-15% it got.

 

[DavidC1]

50% faster than LNL like i said sadly bottlenecked by memory

Pantherlake's Xe3 improves greatly on Depth Writes micro benchmark, which is related to the occlusion culling technology in the GPU, thus it will improve bandwidth utilization efficiency.

 

[Joe NYC]

Also again, what about cost? 18A should be much cheaper for Intel than corresponding dies from TSMC (now that the process tech is already available, i.e. after sunk cost for Intel). So profit per CPU should be higher for Intel going forward.

re: costs

1. Intel will need to start full depreciation and pay full operational cost for the Arizona fab, which has been kept "off the books" mostly. Starting with a low number of wafers with low yields will actually make things much worse at the beginning. Ramping new node is always costly. In the short run, the costs will go much higher. Perhaps even 5x the TSMC prices while fab is operating at extremely low rate of utilization and efficiency.

Intel predicted fab breakeven in 2027, so 2 years from now. It will take the fab running at close to 100% utilization, and high yields for it to be profitable.

2. Comparing costs of Lunar Lake vs. Panther Lake may be a mistake. Intel needs to replace Raptor Lake with Panther Lake. The costs are going to go up either way, with MTL, LNL or PTL.

 

[DavidC1]

2. Comparing costs of Lunar Lake vs. Panther Lake may be a mistake. Intel needs to replace Raptor Lake with Panther Lake. The costs are going to go up either way, with MTL, LNL or PTL.

Intel's case is a bit special in that they relied too much on multi-patterning DUV for Intel 7 process, thus the cost increase going to 18A will be relatively less compared to TSMC where they moved to EUV quicker. Having PowerVia also allows relaxing of pitches a bit(or not having to make it tighter) which means lithography wise it'll be simpler, partially cancelled out by the increased process steps.

From Tomshardware:

First things first: Intel emphasized that Xe3 is not based on the Celestial architecture,

 

[Henry swagger]

Intel's case is a bit special in that they relied too much on multi-patterning DUV for Intel 7 process, thus the cost increase going to 18A will be relatively less compared to TSMC where they moved to EUV quicker. Having PowerVia also allows relaxing of pitches a bit(or not having to make it tighter) which means lithography wise it'll be simpler, partially cancelled out by the increased process steps.

From Tomshardware:

Intel high performance cells always out perform tsmc hp cells tsmc just has better high density

 

[DavidC1]

So ARC 140V gets ~4000 in TimeSpy. 70% gets us to 7000, meaning GTX 1080 levels. That's quite amazing, in a 28-35W power envelope including CPU.

 

[511]

So ARC 140V gets ~4000 in TimeSpy. 70% gets us to 7000, meaning GTX 1080 levels. That's quite amazing, in a 28-35W power envelope including CPU.

Still less bandwidth 320GB/s vs 153GB/s which will hold it back

 

[DavidC1]

Still less bandwidth 320GB/s vs 153GB/s which will hold it back

It won't be uniformly equal, but it'll be quite similar in modern workloads where neither can put out many frames and GTX 1080 is basically shader bound. I've seen this before. The dGPUs can put out many fps especially in older titles(because iGPU has to share CPU as well limiting peak fps), but they become close in modern titles.

Xe3 also has other advantages such as the large cache.

 

[Joe NYC]

Intel's case is a bit special in that they relied too much on multi-patterning DUV for Intel 7 process, thus the cost increase going to 18A will be relatively less compared to TSMC where they moved to EUV quicker.

After all the years of Intel being more or less on the same node, you would think they would improve the yield high enough, so that the only cost overhead would be having to multi-patterning. Intel presumably has enough DUV equipment (capacity) to accomplish it, so it is just using the existing equipment.

Having PowerVia also allows relaxing of pitches a bit(or not having to make it tighter) which means lithography wise it'll be simpler, partially cancelled out by the increased process steps.

In theory, it should be increasing the yields and performance, but in practice, it is not (yet). Then all you end up is higher cost of more processing steps.

The cost is not just that of the CPU die. There are dies still coming from TSMC for the IO and the big GPU. Plus there is cost of packaging. All in all making the cost of PTL >> the cost of RPL. Even the low cost Wildcat will have a cost problem vs. RPL.

Historically, Intel has always warned about cost of ramping a new node, and historically, shifted those costs to server product division, which had very high margins, high revenue and was able to absorb these costs.

Now, the ramp up costs may be even higher, and no high margin division to hide the costs in. Since the internal split of foundry / product is just a thin line, Intel can shift these costs just by having "Foundry" charge "Products" higher or lower price as desired, depending on which part of the business Intel wants to look better. So we may never get the full answer.

 

[adroc_thurston]

Even the low cost Wildcat will have a cost problem vs. RPL

naa

 

[DavidC1]

After all the years of Intel being more or less on the same node, you would think they would improve the yield high enough, so that the only cost overhead would be having to multi-patterning. Intel presumably has enough DUV equipment (capacity) to accomplish it, so it is just using the existing equipment.

That's why computer prices have reversed the trend and is increasing, when in the true Golden Age of Moore's Law, computer prices plummetted. Dell ads used to have $3-7K PCs.

In theory, it should be increasing the yields and performance, but in practice, it is not (yet). Then all you end up is higher cost of more processing steps.

I'm not sure if it ever promised increased yields. I think it's just something they are saying. So for example they could use PowerVia all for density(meaning same pitches), or all for simplicity(maximum relaxation meaning zero density gain). Designs can theoretically be simpler, but that's again their choice. It's like thinking Ruby power supply systems are going to use less power, but in reality it's the Bronze PS systems that use less power, because they never needed the efficiency anyway. Servers that use 1000W just for GPUs and run 24/7 need every bit. Your ma and pa system on internet browsing doesn't.

The cost is not just that of the CPU die. There are dies still coming from TSMC for the IO and the big GPU. Plus there is cost of packaging. All in all making the cost of PTL >> the cost of RPL. Even the low cost Wildcat will have a cost problem vs. RPL.

Alderlake-N is already a two die solution. So Wildcat Lake won't be special in that regard. Jasperlake was a monolithic die. Same with AMD and their countless chiplets on die.

Historically, Intel has always warned about cost of ramping a new node, and historically, shifted those costs to server product division, which had very high margins, high revenue and was able to absorb these costs.

It's more about the slowly declining volume. Remember what Otellini told Jobs about the iPhone deal (paraphrasing): "I don't think your volume is high enough for the low cost you are asking for". So he was saying if he knew how successful(volume) it was, then he would have said yes no question asked.

The reason volume is important, is because fixed costs are always there, even if you make just 1 chip, or you make 1 million. So the warning is about the fixed costs moving to a new node with new equipment and changing equipment. If you sell 10 billion units, even 5% margin is acceptable. If you are selling just 10 of them, you better make something to charge $10 million for each and at 95% margin at least!

But, I also think the companies are being hyperbolic about costs, because Nvidia for example complained many times, yet their revenues are also skyrocketing.

 

[Joe NYC]

Alderlake-N is already a two die solution. So Wildcat Lake won't be special in that regard. Jasperlake was a monolithic die. Same with AMD and their countless chiplets on die.

I don't think Intel is using Foveros packaging for Alder Lake N. Just 2 chips on substrate, as far as I can tell.

It's true that costs will go down, but with Foveros, they are starting from a much higher base.

 

[511]

Wish they had

After all the years of Intel being more or less on the same node, you would think they would improve the yield high enough, so that the only cost overhead would be having to multi-patterning. Intel presumably has enough DUV equipment (capacity) to accomplish it, so it is just using the existing equipment.

It is not cheap though to do quad patterning

But, I also think the companies are being hyperbolic about costs, because Nvidia for example complained many times, yet their revenues are also skyrocketing.

They are in the boon they can pass almost all of their cost to customers.

Alderlake-N is already a two die solution. So Wildcat Lake won't be special in that regard. Jasperlake was a monolithic die. Same with AMD and their countless chiplets on d

It is simply 18A die + PCH on N6 with UCI-E for RPL-