Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Geddagod]

TPU.

Unless you think Pantherlake clocks at 5.6GHz, the performance graphs also support this.

Lmao alr I got fact checked. Thanks. This is a good point.

 

[dullard]

Yes, that slide comes out of nowhere and even the coloring compared to previous slides seems to imply the rose bars are for Panther Lake, when in reality it's just about driver updates on Lunar Lake.

There were over a dozen presentations each with different colored slides. That particular slide is in their platform tuning section of the low power gaming presentation.

Since the previous two slides in the deck were related to CPU spikes leading to GPU throttling and thus stuttering, showing a need for clock balancing, I have to assume that graph is related to tuning to avoid GPU throttling. In other words, it is comparing their chips with and without tuning (not comparing one chip generation to another).

 

[Meteor Late]

Efficiency doesn't look too bad, but 18A is a bust at the higher end of the curve basically. This is N3 class node competitor basically, as many predicted correctly, without going into semantics if N3E or N3P.
We also need to remember, in regards to efficiency, N3B was a disappointing node overall, we saw it with the efficiency Apple got out of it with their chip implementation.
Simply put, 5.1GHz with a supposedly N2 node competitor, even N3P node competitor, is just bad. Efficiency being better is just N3B being a below average node, 18A is probably N3P class in terms of efficiency at lower end, N5-ish class in terms of peak performance and worse than TSMC in terms of yields.

18A is a failure basically, not a complete failure, but a failure nonetheless.

 

[Geddagod]

Efficiency doesn't look too bad, but 18A is a bust at the higher end of the curve basically. This is N3 class node competitor basically, as many predicted correctly, without going into semantics if N3E or N3P.
We also need to remember, in regards to efficiency, N3B was a disappointing node overall, we saw it with the efficiency Apple got out of it with their chip implementation.
Simply put, 5.1GHz with a supposedly N2 node competitor, even N3P node competitor, is just bad. Efficiency being better is just N3B being a below average node, 18A is probably N3P class in terms of efficiency at lower end, N5-ish class in terms of peak performance and worse than TSMC in terms of yields.

18A is a failure basically, not a complete failure, but a failure nonetheless.

I think reading too much into Fmax for a node comparison is harsh, because we have seen how binning and ramping volume can massively help increase Fmax.

 

[Meteor Late]

I think reading too much into Fmax for a node comparison is harsh, because we have seen how binning and ramping volume can massively help increase Fmax.

As if Intel is not binning with the top Panther Lake chip lol

 

[ToTTenTranz]

Gamers Nexus published a video focused on Panther Lake's iGPU:

In this particular case that apparently refers to a frame from Cyberpunk 2077 and if we assume it's a "median frame", Lunar Lake is getting 22FPS while Panther Lake gets 43.7FPS.

 

[Geddagod]

As if Intel is not binning with the top Panther Lake chip lol

They don't have yields (yet).

 

[João Bortolace]

P core looks smaller than before

https://twitter.com/x/status/1976310937763148111

 

[Geddagod]

P core looks smaller than before

https://twitter.com/x/status/1976310937763148111

That was the rumor. Unfortunately the resolution is sooo low that it's hard to say anything all that conclusively. Not that will stop anyone (including maybe me later lol) from trying.

 

[Saylick]

I think reading too much into Fmax for a node comparison is harsh, because we have seen how binning and ramping volume can massively help increase Fmax.

Well, considering 18A uses GAAFET and PowerVia BSPDN, it’s got all the cutting edge bells and whistles yet is barely holding on in the cutting edge node race.

 

[Geddagod]

Well, considering 18A uses GAAFET and PowerVia BSPDN, it’s got all the cutting edge bells and whistles yet is barely holding on in the cutting edge node race.

Dont forget it was supposed to use high NA EUV too haha. Really did get all the bell and whistles.
Who knows though, TSMC seems to have delayed their BSPD implementation (N2P > A16), so maybe this head start will actually net them something.
Though this strategy didn't really work out for Samsung for GAA.

 

[DavidC1]

Efficiency doesn't look too bad, but 18A is a bust at the higher end of the curve basically. This is N3 class node competitor basically, as many predicted correctly, without going into semantics if N3E or N3P.
We also need to remember, in regards to efficiency, N3B was a disappointing node overall, we saw it with the efficiency Apple got out of it with their chip implementation.
Simply put, 5.1GHz with a supposedly N2 node competitor, even N3P node competitor, is just bad. Efficiency being better is just N3B being a below average node, 18A is probably N3P class in terms of efficiency at lower end, N5-ish class in terms of peak performance and worse than TSMC in terms of yields.

What? The CPU looks good. It's 15% faster in MT at same power, or 40% less power at same performance(meaning, 35W = 55W). You won't get that with just CPU changes, it's mostly node.

4+8 paired with 4LPE cores manages to be 15% faster at peak performance over a 6+8 part.

P core looks smaller than before

https://twitter.com/x/status/1976310937763148111

It doesn't have enough detail to determine with any accuracy. If you take the E core and divide by 4, you get 2.5x the difference from the P. While that IS smaller versus the 3x, that's well within the margin of error difference on a terrible shot, which this is.

I think the ratio will be mostly same between the two core types, with the P core doing relatively better perf/area wise because Lion Cove needed optimizations. So you go from 10% difference per/clock + 3x size to 12-15% difference + 3x size.

Well, considering 18A uses GAAFET and PowerVia BSPDN, it’s got all the cutting edge bells and whistles yet is barely holding on in the cutting edge node race.

While it's a fair point, since the competitor does not have them, it has to stand on a "black box" standpoint, meaning how does it fair against competing products coming at a similar timeframe?

 

[regen1]

It's kinda confirmed, no actual product on shelves this year.
All SKUs will launch 2026

 

[dullard]

Dont forget it was supposed to use high NA EUV too haha. Really did get all the bell and whistles.

Didn't intel drop high-NA EUV for 18A?

 

[Saylick]

Didn't intel drop high-NA EUV for 18A?

They did. 18A does not use High-NA from what I remember.

 

[511]

We also need to remember, in regards to efficiency, N3B was a disappointing node overall, we saw it with the efficiency Apple got out of it with their chip implementation.

N3B was good at low power levels it sucked at higher voltage for Desktop

Dont forget it was supposed to use high NA EUV too haha. Really did get all the bell and whistles.

They are doing weird testing with High NA though like replacing some step in 18A with HNA or something like that from one of their presentation somewhere

Though this strategy didn't really work out for Samsung for GAA.

samsung GAA has only made 17mm2 chip

 

[dullard]

P core looks smaller than before

https://twitter.com/x/status/1976310937763148111

That annotation has the P core's L2 swapped (on outer edges) from the location where Intel's graphic puts it (inner edge along L2 cache). Probably won't make much difference on the size, but the annotation starting off wrong does not bode well for using the annotation as rough estimates of size.

 

[Geddagod]

N3B was good at low power levels it sucked at higher voltage for Desktop

N3B wasn't even good at that- look how mid the A17 uplift was over edit: A16 not A18 lol perf/watt. That really was the first alarm bells tbh.

samsung GAA has only made 17mm2 chip

Exynos 2500 is on Samsung 3nm. Way bigger.

 

[Saylick]

While it's a fair point, since the competitor does not have them, it has to stand on a "black box" standpoint, meaning how does it fair against competing products coming at a similar timeframe?

Fair enough. Let's see...

Assuming the P cores don't have an IPC gains, Intel 18A nets about 10% higher Fmax than N3B and >30% lower power at the same ST performance.

I was trying to dig around to understand what TSMC claimed for N3B --> N3E --> N3P and found this:

Assuming N3 refers to N3B in this figure, this puts 18A somewhere between N3E (-32% power at same perf vs. N3B) and N3P (between -35% and -39% power at same perf vs. N3B).

In terms of launch schedule, N3E was used in Apple SoCs in H2 2024 and N3P will be used in Apple SoCs in H2 2025, although HVM was already happening in H1 2025. N2 and A16 is slated for HVM for H2 2026.

Based on this, it seems to imply 18A somewhere between N3E and N3P in terms of perf/W and it comes out >6 months behind the equivalent TSMC node's HVM date. All this on a node that already taps into the benefits of GAAFET and BSPDN.

 

[Covfefe]

Fair enough. Let's see...

Assuming the P cores don't have an IPC gains, Intel 18A nets about 10% higher Fmax than N3B and >30% lower power at the same ST performance.

I was trying to dig around to understand what TSMC claimed for N3B --> N3E --> N3P and found this:
View attachment 131717
Assuming N3 refers to N3B in this figure, this puts 18A somewhere between N3E (-32% power at same perf vs. N3B) and N3P (between -35% and -39% power at same perf vs. N3B).

In terms of launch schedule, N3E was used in Apple SoCs in H2 2024 and N3P will be used in Apple SoCs in H2 2025, although HVM was already happening in H1 2025. N2 and A16 is slated for HVM for H2 2026.

Based on this, it seems to imply 18A somewhere between N3E and N3P in terms of perf/W and it comes out >6 months behind the equivalent TSMC node's HVM date. All this on a node that already taps into the benefits of GAAFET and BSPDN.

That second column is mislabeled. The header should be "N3E vs N5". N3E is not 32% lower power than N3B.

A correct chart from an archived Anandtech article can be found here:

https://web.archive.org/web/20250114111527/https://www.anandtech.com/show/18833/tsmc-details-3nm-evolution-n3e-on-schedule-n3p-n3x-deliver-five-percent-gains

 

[hemedans]

samsung GAA has only made 17mm2 chip

E2500 exist, not much volume though

 

[Saylick]

That second column is mislabeled. The header should be "N3E vs N5". N3E is not 32% lower power than N3B.

A correct chart from an archived Anandtech article can be found here:

https://web.archive.org/web/20250114111527/https://www.anandtech.com/show/18833/tsmc-details-3nm-evolution-n3e-on-schedule-n3p-n3x-deliver-five-percent-gains

OK, well that makes a BIG difference!

 

[511]

Assuming N3 refers to N3B in this figure, this puts 18A somewhere between N3E (-32% power at same perf vs. N3B) and N3P (between -35% and -39% power at same perf vs. N3B).

you calculated wrong and the column is wrong

 

[Saylick]

you calculated wrong and the column is wrong

Thanks for letting me know. @Covfefe pointed it out already one post above.

 

[ondma]

also 18A looks fine to me View attachment 131712

Means nothing without numbers on the axes.