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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

Senior member
Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

Intel Raptor Lake UIntel Wildcat Lake 15WIntel Lunar LakeIntel Panther Lake 4+0+4
Launch DateQ1-2024Q2-2026Q3-2024Q1-2026
ModelIntel 150UIntel Core 7 360Core Ultra 7 268VCore Ultra 7 365
Dies2223
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6Intel 18-A + Intel 3 + TSMC N6
CPU2 P-core + 8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-cores4 P-core + 4 LP E-cores
Threads12688
Max Clock5.4 GHz4.8 GHz5 GHz4.8 GHz
L3 Cache12 MB6 MB12 MB12 MB
TDP15 - 55 W15 - 35 W17 - 37 W25 - 55 W
Memory128-bit LPDDR5-520064-bit LPDDR5x-7467128-bit LPDDR5x-8533128-bit LPDDR5x-7467
Size96 GB48 GB32 GB128 GB
Bandwidth83 GB/s60 GB/s136 GB/s120 GB/s
GPUIntel GraphicsIntel GraphicsArc 140VIntel Graphics
RTNoNoYESYES
EU / Xe96 EU2 Xe8 Xe4 Xe
Max Clock1.3 GHz2.6 GHz2 GHz2.5 GHz
NPUGNA 3.017 TOPS48 TOPS49 TOPS






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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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The Xe Media Engine with Panther Lake does add 10-bit AVC encode/decode, 10-bit AV1 encode and decode, and Sony XAVC-H / XAVC-HS / XAVC-S encode and decode.
 
There's a whopping 16MB L2 in there meaning they increased the L2 per core by 50%, and then it can access up to 18MB L3 on the Compute Tile.
Adding to this, there's also 8MB memory-side cache which may increase effective bandwidth out of the 153.6GB/s LPDDR5X.




This isn't Xe2 vs Xe3. It's Xe2 (Arv 140V) with the power tuning patch on MSI Claw.
Yes, that slide comes out of nowhere and even the coloring compared to previous slides seems to imply the rose bars are for Panther Lake, when in reality it's just about driver updates on Lunar Lake.
 
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That's not what the graph is saying.
1760018875268.png
yeah but if you look hard enough not much improvement
Looks like it’s around N3E/N3P performance based on how it stacks up with N3B? Which has been what TSMC believed it would be from the beginning.
I was always expecting between N3P and N2 tbh and it seems like that N3B was between N5 and N3E so this means that which is far better tbh and perfectly servicable
 
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yeah but if you look hard enough not much improvement
That's still a few %, which is really good if the claims of Lunarlake efficiency is true. They can replace both effectively, while keeping the P cores at 4. Unless the clock speeds are higher than 5.1GHz, 5-10% perf/clk improvements are very reasonable. It's between Tick and Tock, Tick never got branch prediction improvements.

I expect a bit less for Darkmont, in the low single digit, but probably improved power efficiency. I don't think beating 6+8 Arrowlake parts are possible without that. This will probably improve P core's area efficiency because it sounds like the gains are rather big for comparatively small changes, meaning it was a targetted change fixing problems in Lion Cove.

It looks like Stephen Robinson is talking for both cores? Maybe they are already taking some responsibilities away.
Adding to this, there's also 8MB memory-side cache which may increase effective bandwidth out of the 153.6GB/s LPDDR5X.
I think this is just low power play again. Lunarlake's MLC offered almost nothing in terms of performance.


-Darkmont's power/perf graph is steeper compared to Skymont in the Raptorlake comparison. Meaning higher performance at lower power.
-40% perf/W improvement for graphics is good, since N3E isn't a huge improvement over N3B. Architecturally it's 25-30% better ISO-process over Xe2.
 
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Looks like it’s around N3E/N3P performance based on how it stacks up with N3B? Which has been what TSMC believed it would be from the beginning.
Depends on what you mean by performance. The clock ceiling of panther lake is no better than lunar lake. Which implies 18A is slightly worse than N3E/N3P for high clock speeds.

However, the power consumption of panther lake is reportedly >30% lower than arrow lake at the same performance. Which implies that 18A is more efficient than N3E/N3P.
 
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Branding Xe3 under "B-series" can be somewhat confusing.

For the upcoming client products PTL, WCL, NVL and potential dGPUs:

Vanilla Xe3 is supposed to be used in iGPUs of
Panther Lake, WildCat Lake, NVL Desktop and -HX SKUs,
NVL-(U?) 4+0+4 compute tile SKUs and
may be some NVL-H(4+8+4 compute tile) SKUs in a similar fashion to PTL.

The 4Xe3 GPU tile(Intel 3 node) used in PTL line should be re-used in NVL Desktop and HX SKUs, NVL-(U?) 4+0+4 compute tile and may be some NVL-H(4+8+4 compute tile) SKUs

Xe3P is supposed to come with some NVL-H SKUs(up to 12Xe3P),
NVL-AX(Halo, if it launches), and discrete GPUs(if it launches).

Xe3P should be a significant upgrade over vanilla Xe3.
 
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