Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Gideon]

Yeah, the amount of bad press coming in such a short timeframe did look suspicious, grounded or not.

It's been clear since last summer that the contingent within Intel that wants to give up manufacturing has been strategically leaking info to Reuters to drive their narrative. It started out with with the "Broadcom doesn't like 18A" and "Intel missed out on PS6" stories, both of which were dubious in the framing of some of the information presented, that paved the way for Gelsinger's dismissal and has continued since.

Now, just because there seems to be a goal behind that constant stream of stories doesn't mean they're not accurate. But the good thing with this one is that if it's true, PTL cannot and will not launch near its planned window.

 

[jpiniero]

Well... what matters is what the salvagability is of Panther Lake. In particular the 5 model. If yields were bad, they could just cut the core count of the 5 model and maybe also do a 3 model (or even "Intel Processor")

Although Arrow and Lunar didn't cut the core count. Course that's likely because they were fabbed at TSMC.

 

[511]

Although Arrow and Lunar didn't cut the core count. Course that's likely because they were fabbed at TSMC.

225H?
LNL 7 core iGPU/5 Core NPU in U5

 

[DrMrLordX]

10% PTL yields by the summer sounds so catastrophically low I don't even know how they could launch PTL (even in limited volume) by early 2026 if it's an accurate figure.

10% yields on such small dice would be catastrophically-bad. That's probably worse than the Ice Lake-SP situation. Anything 40% and below means setting wafers on fire just to get product out the door.

 

[511]

That's a repeat of 10nm lol 😂

 

[511]

From TPU

 

[Magio]

10% yields on such small dice would be catastrophically-bad. That's probably worse than the Ice Lake-SP situation. Anything 40% and below means setting wafers on fire just to get product out the door.

And hell, back with Ice Lake at least they had DUV capacity to brute force once they really wanted product out the door. They already have limited EUV wafers, there is no way to deliver PTL at any sort of scale with yields like that.

And not delivering PTL means screwing their OEM partners whose 2026 plans all hinge on this, which in turns blows the door wide open for AMD and Qualcomm to take over in that space.

If this is accurate, Intel is several orders of magnitude more screwed than we thought they were.

 

[Kepler_L2]

10% PTL yields by the summer sounds so catastrophically low I don't even know how they could launch PTL (even in limited volume) by early 2026 if it's an accurate figure.

They did it with Ice Lake

 

[jpiniero]

They did it with Ice Lake

They did have a lot more 10 nm capacity then tho.

 

[adroc_thurston]

PTL cannot and will not launch near its planned window.

Mind that the 'planned' PTL launch is the meme volume 12 gfx core SKU.

 

[DavidC1]

It's been clear since last summer that the contingent within Intel that wants to give up manufacturing has been strategically leaking info to Reuters to drive their narrative. It started out with with the "Broadcom doesn't like 18A" and "Intel missed out on PS6" stories, both of which were dubious in the framing of some of the information presented, that paved the way for Gelsinger's dismissal and has continued since.

Reuters have been in hype news mode for a while now. While there could be bits of truth, such sensationalist articles all the time loses trust in the overall publication over time.

Only time will tell.

 

[branch_suggestion]

18A parametric yield is horrible. This is no secret, many sources have been saying the defect rate is fine, but the clocks are very not fine.
To the guy who ran away from here, your "higher performance than N2" node doesn't get any of the parts that actually clock high.
Those are on N2 Nanoflex, the actual highest performance node on the planet surpassing any Intel node in clocking potential even at lower Vmax.
It is an alright node for lower end mobile parts I guess. Same issues as Ice Lake basically.

 

[DavidC1]

Same issues as Ice Lake basically.

Not just Icelake, but Cannonlake. That the defect rate was acceptable but parametric yield was bad. If you take a look at the released parts, it had to be downclocked, meaning it couldn't clock as high.

Then there was strange rumors like iGPU needing to be disabled. Since GPUs are more repetitive structures it doesn't point to defect rates.

If true, this would explain why Novalake is using N2 on high end desktop.

It is an alright node for lower end mobile parts I guess.

The issue with this is even on 18A it sucks more on mobile, so when you are saying mobile you are talking laptops, meaning on tablets/phones it's even worse since they can't meet their own goals.

Short of a huge breakthrough, 14A being cancelled seems like a done deal.

 

[511]

They did it with Ice Lake

Who is going to subsidize the node though in ice lake era they were in a better position financially and in terms of control.
It's gonna cause them a huge loss also surely the layoffs didn't affect the yield.

 

[branch_suggestion]

Not just Icelake, but Cannonlake. That the defect rate was acceptable but parametric yield was bad. If you take a look at the released parts, it had to be downclocked, meaning it couldn't clock as high.

Oh no Cannonlake was <10% parasitic yield, the only part shipped was ~100k i3 garbo bins to China.
OG 10nm was worse than A0 Fermi.
This isn't remotely that bad, PTL has lots of errata from design issues with the early PDK but those should be resolved by the production stepping.
The clocks are stuck below 5Ghz, that is the big issue.

 

[511]

The clocks are stuck below 5Ghz, that is the big issue.

No halo products they will sell I5 as long as it's 4.5-4.8ish range there will be no other way.

 

[DavidC1]

Oh no Cannonlake was <10% parasitic yield, the only part shipped was ~100k i3 garbo bins to China.

Was it actually under 10% or hearsay, because I heard both arguments.

No halo products they will sell I5 as long as it's 4.5-4.8ish range there will be no other way.

One one side some are expecting NVL to reach 6.5GHz+ while not answering how it works with the >10% ST gains

While on the other side, we're expecting i5's to be under 5GHz, which would be a record difference in SKUs.

I think a more reasonable explanation is NVL doesn't clock higher than Arrowlake.

 

[511]

Was it actually under 10% or hearsay, because I heard both arguments.

Cannon Lake sucked in Both D0 and Parametric it was a disaster of a node.

 

[511]

One one side some are expecting NVL to reach 6.5GHz+ while not answering how it works with the >10% ST gains

Cause that part is on N2

While on the other side, we're expecting i5's to be under 5GHz, which would be a record difference in SKUs.

PTL SKU also i5 have mostly been under 5Ghz on mobile(not counting HX).

think a more reasonable explanation is NVL doesn't clock higher than Arrowlake.

This is on N2 so if they doesn't hit 6+ GHz it's a failure in design.

 

[DavidC1]

This is on N2 so if they doesn't hit 6+ GHz it's a failure in design.

No, it's a failure in design if a part that clocks 10% higher performs >10% higher.

Cannon Lake sucked in Both D0 and Parametric it was a disaster of a node.

That does qualify as a disaster, especially when node gains are shrinking.

 

[adroc_thurston]

This is on N2 so if they doesn't hit 6+ GHz it's a failure in design.

Intel cores are chungus.

No, it's a failure in design if a part that clocks 10% higher performs >10% higher.

?

 

[DavidC1]

?

Netburst 2.0. New uarch that aims at performance increase solely from clockspeed.

 

[511]

Intel cores are chungus.

Oh definetly lol chungus core with fused off hardware the equalizer

 

[adroc_thurston]

New uarch that aims at performance increase solely from clockspeed.

So, Apple M4?

 

[QuickyDuck]

PTL 10% yield is for i9
CNL <10% yield is for i3

Two very different story