Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[LightningZ71]

Intel slammed head long into two problems: because 10nm was delayed, they ran into the fiscal limits of total transistors they could sell on a single die. Rocket Lake, among it's other issues, lost cores as compared to Comet Lake as a result. They also ran into the problem of maximizing MT throughput in the face of massive power consumption with Alder and Raptor Lake. Without chiplet and multiple die, they were having to spam small cores and dump massive power into that one die to get competitive performance. When held to the same power limits as AMD's similar parts, they suffered in MT performance.

 

[igor_kavinski]

Hopefully they do something smart for Arrow Lake Refresh, like 4P+32E or something.

 

[sgs_x86]

Hopefully they do something smart for Arrow Lake Refresh, like 4P+32E or something.

I think they are better off with an updated SoC tile that enables faster fabric clocks and has memory side cache.

 

[DavidC1]

Without chiplet and multiple die, they were having to spam small cores and dump massive power into that one die to get competitive performance. When held to the same power limits as AMD's similar parts, they suffered in MT performance.

Chiplets would have merely masked the problem that they had an inefficient core that took significantly more area than competing P cores. What was the difference between Golden and Zen 4? Like 1.7x?

The design team has been masked for many, many years because the process team was so ahead. It only got exposed recently because it's still been fairly recent when they lost the process lead. I have to wonder how Core 2 and Nehalem would have done if it was on the same process as used by AMD of those days.

I think they are better off with an updated SoC tile that enables faster fabric clocks and has memory side cache.

Memory side cache will only really help for power. Otherwise it's just L4 cache, and if you can make that fast, it's better to skip that and speed up the L3 cache instead.

 

[511]

Chiplets would have merely masked the problem that they had an inefficient core that took significantly more area than competing P cores. What was the difference between Golden and Zen 4? Like 1.7x?

The design team has been masked for many, many years because the process team was so ahead. It only got exposed recently because it's still been fairly recent when they lost the process lead. I have to wonder how Core 2 and Nehalem would have done if it was on the same process as used by AMD of those days.

Memory side cache will only really help for power. Otherwise it's just L4 cache, and if you can make that fast, it's better to skip that and speed up the L3 cache instead.

RWC is 5.33 counting 2MB L2 without SRAM it is 3.752mm2 on Intel 4.
Zen 4 is 3.84 mm2 with 1MB L2 on N5

 

[DavidC1]

RWC is 5.33 counting 2MB L2 without SRAM it is 3.752mm2 on Intel 4.
Zen 4 is 3.84 mm2 with 1MB L2 on N5View attachment 117910

Zen 4 is 2.56mm2 without L2. RWC is 50% larger at practically the same performance.

Also, Zen 5 is 2.7mm2 on N4 while Lion Cove is 3.4mm2 on N3B, the densest version of N3.

 

[511]

Zen 4 is 2.56mm2 without L2. RWC is 50% larger at practically the same performance.

Also, Zen 5 is 2.7mm2 on N4 while Lion Cove is 3.4mm2 on N3B, the densest version of N3.

LNC Doesn't have HT btw RWC Does

 

[eek2121]

Yeah IMO Intel needs a new design. They seem to be at their limits on the P core. The E core design seems to be better, but it lacks clocks and/or IPC.

 

[511]

Yeah IMO Intel needs a new design. They seem to be at their limits on the P core. The E core design seems to be better, but it lacks clocks and/or IPC.

Hence the unified core I think royal cove was bad design from the initial rumors it was way too big for the MT performance/Area

 

[DrMrLordX]

Hence the unified core I think royal cove was bad design from the initial rumors it was way too big for the MT performance/Area

Royal Core was allegedly aimed at high performance when running interpreted languages and/or JVM stuff. Like Zen5 but even more extreme.

 

[511]

Royal Core was allegedly aimed at high performance when running interpreted languages and/or JVM stuff. Like Zen5 but even more extreme.

Yes but it was so wide that it didn't clock much and costed too much area.

 

[igor_kavinski]

The E core design seems to be better, but it lacks clocks and/or IPC.

Mainly clocks. See the crazy screenshot here: https://forums.anandtech.com/thread...akes-discussion-threads.2606448/post-41401242

 

[DavidC1]

Yeah IMO Intel needs a new design. They seem to be at their limits on the P core. The E core design seems to be better, but it lacks clocks and/or IPC.

At 3x the core size difference it doesn't really matter. Lion Cove performs merely 10% faster per clock in average as well.

Just like ARM cores and Apple cores having a better uarch will make up for clockspeed difference. Just expanding the core size to be same size as Lion Cove would far outperform it.

@511 Yea, even more embarassing for Lion Cove.

 

[511]

At 3x the core size difference it doesn't really matter. Lion Cove performs merely 10% faster per clock in average as well.

Just like ARM cores and Apple cores having a better uarch will make up for clockspeed difference. Just expanding the core size to be same size as Lion Cove would far outperform it.

@511 Yea, even more embarassing for Lion Cove.

I have been saying that after seeing the benchmark for skymont and Lion cove and their Area it is better to scale up Skymont starting Nova Lake there will be ISA Parity as well as Skymont is getting native 256 bit ports APX/AVX10.2/256

 

[jdubs03]

I have been saying that after seeing the benchmark for skymont and Lion cove and their Area it is better to scale up Skymont starting Nova Lake there will be ISA Parity as well as Skymont is getting native 256 bit ports APX/AVX10.2/256

They have to realize this themselves. Ideally they’ll understand this for Nova Lake or the next gen, but better be the former.

 

[MS_AT]

Skymont is getting native 256 bit ports APX/AVX10.2/256

Are you sure it will be native, I mean 256b exec units and not 128b units teaming up or executing in sequence like Zen4?

 

[511]

Are you sure it will be native, I mean 256b exec units and not 128b units teaming up or executing in sequence like Zen4?

Yes I think it was Kepler who said that In this forum lol

They have to realize this themselves. Ideally they’ll understand this for Nova Lake or the next gen, but better be the former.

They realized it last year with skymont and started Unified cove pending in 2027-28.

 

[msj10]

P cores are here to stay for at least 3 more generations with Cougar Cove Panther Cove and Griffin Cove so Unified Core is 2028 at best if it doesn't get delayed or even cancelled.

 

[511]

I don't think something that will save money in the future and is a crucial aspect of the business would be cancelled but it's Intel cancel culture is insane.

 

[igor_kavinski]

P cores are here to stay for at least 3 more generations with Cougar Cove Panther Cove and Griffin Cove so Unified Core is 2028 at best if it doesn't get delayed or even cancelled.

Griffin Cove sounds scary. I wonder if the Unified Core will be hardly 5% faster (like Arrow Lake) but obviously the Unified Core should win in efficiency.

 

[511]

Griffin Cove sounds scary. I wonder if the Unified Core will be hardly 5% faster (like Arrow Lake) but obviously the Unified Core should win in efficiency.

That won't be the case lol

 

[igor_kavinski]

That won't be the case lol

Any juicy leaks?

 

[511]

Any juicy leaks?

Nope I will share when I get some only a hunch 🫠

 

[igor_kavinski]

Nope I will share when I get some only a hunch 🫠

Those don't work with Intel anymore. A lot of people here thought Pat would save Intel and couldn't believe their eyes when they read about his "retirement".

 

[511]

Those don't work with Intel anymore. A lot of people here thought Pat would save Intel and couldn't believe their eyes when they read about his "retirement".

My hunch is on skymont team not Pat this time 🙂