Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[ajsdkflsdjfio]

I might be wrong, but this doesn't sound right at all.
We know part of it is Intel's P core being bad, but if you look at Granite Rapids vs Turin, GNR loses badly in all metrics and has a much lower base frequency. Not all of the difference is architectural imho. At "not 5GHz+" frequencies Intel 3 seems to be inferior to TSMC N4 in many metrics.

Yea isn't it the case that in power constrained scenarios, intel's poorly optimized core design may perform worse regardless of node? You see this same thing in Lion cove where "magically" N3B seems to be inferior to TSMC N4 in many metrics. Ofc arrow lake performance problems are from a myriad of differing issues not just lion cove, but lion cove is still obviously part of the issue of performance stagnation. If lion cove on n3 fails to perform vs zen 5 on n4, why would redwood cove perform any better vs n4 in a server application where power efficiency is paramount when redwood cove is basically a node-shrink of golden-cove from intel 12th generation?

 

[511]

Yes, best performance for like 6 months and then their CPUs would've started degrading...

You know that debacle was a design issue not a process issue the oxidation was mishandling of batches at a fab well TSMC node can't even clock high as intel nodes they would die at way less voltage than Intel's 🤪

 

[511]

I might be wrong, but this doesn't sound right at all.
We know part of it is Intel's P core being bad, but if you look at Granite Rapids vs Turin, GNR loses badly in all metrics and has a much lower base frequency. Not all of the difference is architectural imho. At "not 5GHz+" frequencies Intel 3 seems to be inferior to TSMC N4 in many metrics.

We have Sierra Forest on Intel 3 process that can do 144 Cores 2.7-3Ghz all core at 250W!

 

[igor_kavinski]

You know that debacle was a design issue not a process issue the oxidation was mishandling of batches at a fab well TSMC node can't even clock high as intel nodes they would die at way less voltage than Intel's 🤪

If it simply were an issue with a small number of batches, Intel could've simply recalled the affected CPUs. They went through multiple (more than 3) microcode updates trying to fix whatever issue there was. If I had a grandma who hid her cash under her mattress, I would steal some and buy a 14900KS to test for science and see how well it hits 6.2 GHz with constant workloads and everyday usage for six months. But the general consensus now is not to trust Raptor Bake and Raptor Re-bake

 

[SiliconFly]

.

 

[coercitiv]

You know that debacle was a design issue not a process issue the oxidation was mishandling of batches at a fab

And you think that makes it better?! Mishandling of batches is hardly reassuring for a potential customer.

Zen 5 on Intel nodes would have been great on paper, then would have gotten delayed like all the Intel products on Intel nodes have been for the last couple of years. More performance but zero market relevance.

 

[igor_kavinski]

Thats a very silly comment. Process was never the issue.

Well, I really hope I'm silly because if I'm being silly then we should see Bartlett Lake hitting 6.2 GHz again next year. In which case, I will happily admit to being silly

 

[igor_kavinski]

Zen 5 on Intel nodes would have been great on paper, then would have gotten delayed like all the Intel products on Intel nodes have been for the last couple of years. More performance but zero market relevance.

AMD engineers probably don't want to work so closely with Intel Foundry personnel anyway coz leaking of their trade secrets to Intel Design Centers would come into the picture sooner or later. Intel Foundry needs to become US National Foundry before AMD will risk doing business with them.

 

[511]

Zen 5 on Intel nodes would have been great on paper, then would have gotten delayed like all the Intel products on Intel nodes have been for the last couple of years. More performance but zero market relevance.

I am just talking about theoretical performance.
Delays and intel had been amazing combo for the last few years I can't deny that 🤣

 

[SiliconFly]

.

 

[511]

You should hope so & you can always admit anytime. I'm assuming this so called Bartlett lake is a cpu based on the already outdated RPL on Intel 7, right? If so, then it is going to inherit all the issues related to RPL. And frankly, why on earth would anyone root for such an outdated product like Bartlett Lake which imho shouldn't even exist? An Intel 7 based cpu in 2025? Yikes!

It's a 12 core monolithic CPU

 

[RTX]

Now of course through publicly available TSMC and Intel density figures you would assume this difference would be much larger, but I believe that the on-paper difference between the density of Intel 4/3 nodes and TSMC N3E are largely due to TSMC offering an actually high density library using a 2-1 fin arrangement which is around 32% more dense than their HP high performance library, while Intel 3's "HD" library is only 10% denser than their HP library leading me to believe it isn't prioritizing density as much as TSMC's 2-1 fin=flex offering. Intel markets using their high density(not really) library densities, while TSMC markets their 2-1 fin or even 1-1 true high-density libraries as the face of N3 achieved densities. Either way in reality it is shown that at-least in client computing chip design, TSMC's N3 designs are not all that much denser than intel 4/3 designs especially if you are comparing N3E or N3P versus intel's nodes with only a 10% or less gap (at least in cache density) between intel 4 and N3E/N3P.

Chip density for intel 3 is up to 1.08x vs intel 4 and logic density is up by ~15%. Their 2-fin should've been -2xfin pitch ( 180nm ) instead of -1xfin pitch ( 210nm ). The additional 10% ppw from intel 3-PT should be enough to allow them to do 180nm 2-fin and still gain ppw vs intel 3 210nm.

 

[igor_kavinski]

If so, then it is going to inherit all the issues related to RPL.

It's an RPL REFRESH REFRESH so if the process can handle it, it should theoretically launch with 6 GHz boosts and 6.2 GHz for the halo part.

 

[LightningZ71]

they'll probably relax the density metrics on Intel 7 one more time, just like they did from Alder Lake to Raptor Lake, then Raptor Lake to Raptor Lake Refresh...

 

[511]

they'll probably relax the density metrics on Intel 7 one more time, just like they did from Alder Lake to Raptor Lake, then Raptor Lake to Raptor Lake Refresh...

Nope Intel 7 is done for as a node in terms of development there is nothing new to add

 

[DrMrLordX]

they'll probably relax the density metrics on Intel 7 one more time, just like they did from Alder Lake to Raptor Lake, then Raptor Lake to Raptor Lake Refresh...

More likely they identify the structure that was burning out due to the old voltage spike behavior and change it (if possible) to handle higher voltages so they can go back to the original TVB.

 

[511]

The 12 core die is a new die altogether and it is for networking group so they should pay attention

 

[OneEng2]

Yeah they did.

No they didn't.

No they didn't.

Best xtor performance.

N3e did not exist when the decision was made.

Ok, so let me get this straight ......

Intel decided INTENTIONALLY to abandon their own fabs, pay MORE to have their core processor tile produced at TSMC, and ALSO decided to spend billions of dollars to continue making their own 20A, 18A and 16A processes as well ...... all culminating into the biggest losses in the companies history?

... and they did this by design?

Please explain this logic to me.

 

[OneEng2]

It's an RPL REFRESH REFRESH so if the process can handle it, it should theoretically launch with 6 GHz boosts and 6.2 GHz for the halo part.

My guess is that Intel is done pushing the process and design through the red and into failure modes..... but then I have seen some pretty crazy decisions before.

 

[moinmoin]

Intel decided INTENTIONALLY to abandon their own fabs, pay MORE to have their core processor tile produced at TSMC,

Swan's decision.

and ALSO decided to spend billions of dollars to continue making their own 20A, 18A and 16A processes as well

Pat's decision.

all culminating into the biggest losses in the companies history?

... and they did this by design?

Contracts were already signed. Both Swan and Pat were and are in the position of having to try the best given a bad hand while trying to reach completely different destinations.

 

[DavidC1]

I'd say density wise intel 3 is already comparable to N3.

Redwood cove on intel 4: 5.33 mm^2 (5.33 on semianalysis 5.05 according to reddit post i used for lunar lake) Lion cove from lunar lake on N3B: 4.53
Lion cove has 2.5 mb of l2 cache per core while redwood cove has 2mb. which is a 25 percent increase of 1.25x. Multiply the cache area for Redwood cove by 1.25x to get the theoretical area for 2.5mb l2 cache on intel 4: 1.215 mm^2.

That's cause your analysis is flawed. SRAM scaling is reaching a hard limit, similar to DRAM running into a limit like ten years ago. Also, Lion Cove expanded significantly, hence why it's 4.5mm2. If it was a straight shrink it's probably in the 3.xmm2 range.

Logic scaling shows TSMC has a substantial advantage.

I might be wrong, but this doesn't sound right at all.
We know part of it is Intel's P core being bad, but if you look at Granite Rapids vs Turin, GNR loses badly in all metrics and has a much lower base frequency. Not all of the difference is architectural imho. At "not 5GHz+" frequencies Intel 3 seems to be inferior to TSMC N4 in many metrics.

The P cores are terrible. It requires more power and die area for less performance than the competition.

What you are saying is basically Intel's 65nm process sucked because of Presler. Yet we also had Conroe/Merom, a far superior chip.

Some is likely due to process but mostly it's architecture and implementation. Implementation, in that they're still learning to get the disaggregated thing right, and GNR itself had troubled development, based on how the scaling sucks with just 2P.

 

[DavidC1]

There is a documentary about Centaur called Rise of the Centaur which was somewhat informative and entertaining. But since then Henry retired and the team was sold to Intel and the IP licensed to Zhaoxin.

I guess they were in the same city as the Intel 'mont team at the time too?

It seems Stephen Robinson, the leader of the E core team came little before the purchase. I'm pretty sure it's not a coincidence.

The Centaur team was said to achieve what they did with fraction of the human and financial resources of a typical MPU team. Certainly they can do good when they need to.

In 1995, Centaur Technology set out to prove that a small team of microprocessor engineers could design an affordable x86 processor for the neglected sub-$1000 PC market. At the time, it was a visionary idea. Now, fourteen years later, Centaur has successfully designed the world's smallest x86 processors, has shipped thirteen different parts, and consistently provides the fastest design cycle in the industry-from concept to completion in about 9 months, 1/3 the time of our competitors. Centaur’s relationship with parent company VIA Technologies, the #2 chipset maker in the world after Intel, has positioned us to be the dominant force in bringing PC power to developing nations. New challenges are just ahead for Centaur Technology’s visionary solutions.

 

[ajsdkflsdjfio]

That's cause your analysis is flawed. SRAM scaling is reaching a hard limit, similar to DRAM running into a limit like ten years ago. Also, Lion Cove expanded significantly, hence why it's 4.5mm2. If it was a straight shrink it's probably in the 3.xmm2 range.

Logic scaling shows TSMC has a substantial advantage.

Yea never mind you are right about the SRAM scaling, I looked it up and N3B and N5 and intel4/3 have similar SRAM cell sizes. Still I think intel 4/3 is more impressive than at first glance even though it hasn't really been proved in any real application yet since meteor lake was basically a test platform for all their new technologies. Hopefully panther lake turns out well, it'll be perfect for comparisons between N3 lioncove/skymont vs 18A cougarcove/darkmont. It'll also be the first time that a (hopefully) decent product is released on an intel node other than intel 7.

 

[DavidC1]

Yea never mind you are right about the SRAM scaling, I looked it up and N3B and N5 and intel4/3 have similar SRAM cell sizes.

If you compare the smallest sizes, N3B has a 20% advantage over Intel 4. Which is roughly same as the numbers you calculated.

Still I think intel 4/3 is more impressive than at first glance even though it hasn't really been proved in any real application yet since meteor lake was basically a test platform for all their new technologies. Hopefully panther lake turns out well, it'll be perfect for comparisons between N3 lioncove/skymont vs 18A cougarcove/darkmont. It'll also be the first time that a (hopefully) decent product is released on an intel node other than intel 7.

I'm not sure why anyone is surprised at Intel processes being a performance leader and density laggard. It has always been the case. It has to do with the mentality and vision of that team.

That's why even Intel themselves admit 18A isn't a perfect fit for mobile. I think perf wise even Intel 3 will be very close to N2, but density wise it'll only take maybe N3 to match 18A.

 

[OneEng2]

Swan's decision.


Pat's decision.


Contracts were already signed. Both Swan and Pat were and are in the position of having to try the best given a bad hand while trying to reach completely different destinations.

So you are saying that Arrow Lake, Lunar Lake were both originally targeting using TSMC? That is not at all what I had heard. Do you have a link? Every resource I can find states that Intel originally targeted 20A for these processors and had to go to TSMC OR wait until 18A was ready. The rest is history.

If you compare the smallest sizes, N3B has a 20% advantage over Intel 4. Which is roughly same as the numbers you calculated.

I'm not sure why anyone is surprised at Intel processes being a performance leader and density laggard. It has always been the case. It has to do with the mentality and vision of that team.

That's why even Intel themselves admit 18A isn't a perfect fit for mobile. I think perf wise even Intel 3 will be very close to N2, but density wise it'll only take maybe N3 to match 18A.

If you are correct, that isn't a great strategy IMO. In a server environment, the limiting factor doesn't end up being die size since you can conceivably put as many tiles/CCD's on an SOC as you want and cost is largely not relevant.... but socket power is. Thermal issues and power issues would limit such a design.

In desktop, this is also a losing strategy for a different reason. Die size (cost) is suddenly VERY important. With die size pricing increasing super-linearly (exponentially?) a strategy that doesn't compete in density is a loser IMO.

I do tend to agree with you though that Intel has been targeting max performance from every point of design. At some points in history, they did this to such an extreme that it was comical. I recall joking about what a great space heater P4 was .