Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

I have lost all my respect for HWUnboxed after this "they are saying E cores are a waste of silicon" lmfao 🤣🤣

https://twitter.com/x/status/1860184289373216859

 

[ajsdkflsdjfio]

Those are just figure a,b,c

yea sorry, I meant what are the technologies in each of those figure being depicted. I assume they are different possible transistor innovations right?

 

[RTX]

After 2A or possibly 1A

 

[Thunder 57]

I have lost all my respect for HWUnboxed after this "they are saying E cores are a waste of silicon" lmfao 🤣🤣

https://twitter.com/x/status/1860184289373216859

I thought it was a fair video. The TL;DW version is that Intel would be bad in productivity performance today without the E cores. Then they say that ARL would only be "pretty good" for gaming while the E cores are "a waste of silicon" in that scenario so that was taken out of context. It's at 8:30 in the video. They briefly mention Bartlett Lake to but they seem to think it may be cancelled? First I've heard of that. I don't think it will reach gamers though.

 

[511]

I thought it was a fair video. The TL;DW version is that Intel would be bad in productivity performance today without the E cores. Then they say that ARL would only be "pretty good" for gaming while the E cores are "a waste of silicon" in that scenario so that was taken out of context. It's at 8:30 in the video. They briefly mention Bartlett Lake to but they seem to think it may be cancelled? First I've heard of that. I don't think it will reach gamers though.

Yes but where is the proof E cores are the thing that makes ARL good as for gaming we have seen 1P+16E destroying only P yet they conclude inverse of it

 

[DrMrLordX]

They briefly mention Bartlett Lake to but they seem to think it may be cancelled? First I've heard of that. I don't think it will reach gamers though.

Might wind up being OEM-only or something?

 

[511]

Might wind up being OEM-only or something?

It's for NEX

 

[Thunder 57]

Yes but where is the proof E cores are the thing that makes ARL good as for gaming we have seen 1P+16E destroying only P yet they conclude inverse of it
View attachment 112029

Most people don't want to have to dick around with active CPU's when switching between tasks. Also those 16 E cores are seriously overclocked. They'll do well in multithreaded tasks but what does it take to achieve those clocks? This just looks like cherry picking.

 

[511]

Most people don't want to have to dick around with active CPU's when switching between tasks. Also those 16 E cores are seriously overclocked. They'll do well in multithreaded tasks but what does it take to achieve those clocks? This just looks like cherry picking.

Maybe but if HWUnboxed want to proof that point they are big tech outlet they should clearly test things before making conclusion like saying these.
The power is in image they are literally pulling less power than 8P+16E while delivering higher FPS even OC

 

[poke01]

These E cores will go away by the end of the decade and for good reason too.

 

[511]

These E cores will go away by the end of the decade and for good reason too.

"P Cove" is going away by end of decade and will be replaced by Unified Core base on E cores

 

[igor_kavinski]

Also those 16 E cores are seriously overclocked.

I think the 285Ks are crazy good bins because the E-cores on 245K don't seem to yield more than 200 MHz OC according to reviews.

 

[gdansk]

"P Cove" is going away by end of decade and will be replaced by Unified Core base on E cores

I heard it'll be based on both, actually.

 

[511]

Maybe they will combine best learnings of both we will have to see but the base is E-Core from the rumors i have heard

 

[mzocyteae]

I heard it'll be based on both, actually.

What matters more is people.
Since e-core team seemed to execute better, let e-core guys steer the development is probably better, for whatever design.
There is sufficient time to make a design from scratch.

 

[511]

What matters more is people.
Since e-core team seemed to execute better, let e-core guys steer the development is probably better, for whatever design.
There is sufficient time to make a design from scratch.

Just fund them like they did with their foundries it will be a lot less than what the foundry took.
The US government ain't helping Intel either with the foundries it's going to be a loosing race without government support in either form in long term for Intel
Even Ireland supports Intel better than US 🤣

 

[DavidC1]

What matters more is people.
Since e-core team seemed to execute better, let e-core guys steer the development is probably better, for whatever design.
There is sufficient time to make a design from scratch.

Exactly.

They said Core 2 combined Netburst and Yonah, but in reality they gave up almost everything in Netburst. Trace Cache, Hyperthreading, double pumped simple ALUs, replay, obsessive focus on clocks. They may have took some inspiration for reaching higher clocks. The faster FSB was going to be used regardless so that's a moot point.

Rather than saying Core 2 was a combo, it's more accurate to say it LEARNED from the mistakes Netburst and its philosophy.

I assume the Unified Core will show a clear sign it's a bigger brother of Arctic Wolf. Only thing it might "adopt" is private L2 caches. Wouldn't be surprised at all if the traces of the P cores go away - uop cache, hyperthreading, expansion without thought, too many fast path circuits, and focus on clocks again.

 

[adroc_thurston]

Trace Cache, Hyperthreading, double pumped simple ALUs, replay, obsessive focus on clocks

All that besides ALU gimmicks retvrned in Sandy.

 

[Thunder 57]

All that besides ALU gimmicks retvrned in Sandy.

Since you leave curt responses, I'll leave you a one word answer.

Bunk.

 

[adroc_thurston]

Since you leave curt responses, I'll leave you a one word answer.

Bunk.

Que?
Also he forgot PRFs, which also returned in Sandy.

 

[OneEng2]

I don't really get what you're trying to say here. Yea sure Hz is not as big of a measure of performance in people's minds as it was back then but it still matters, as does IPC which also existed back then. Also ur idea about naming nodes with "model numbers", intel hasn't named their nodes based on actual realistic measures of their transistor technology since 1995:

"Intel held the line from “10 micron” in 1972 through “0.35 micron” in 1995, an impressive 23-year run where the node name matched gate length. Then, in 1997 with the “0.25 micron/250 nm” node they started over-achieving with an actual Lg of 200 nm – 20% better than the name would imply. This “sandbagging” continued through the next 12 years, with one node (130nm) having Lg of only 70nm – almost a 2x buffer. Then, in 2011, Intel jumped over to the other side of the ledger, ushering in what we might call the “overstating decade” with the “22nm” node sporting an Lg of 26 nm."

Naming nodes with numbers that don't technically mean anything is not something new within the past 20 years. Determining what process is "better" is also not related to this discussion at all. The difficulty in determining what node is better than what is because now there is actual competition where Intel isn't the unquestionable leader, and TSMC, although clearly better, is not too far ahead from intel either in terms of pure process technology. In hobbyist discussion boards like this its just conjecture based on the limited marketing materials we have from Intel and TSMC so obviously there is some difficulty in distinguishing exactly how good one process is compared to another, although arguably there is already a decent enough hierarchy established by the more educated people here. Besides it's not hard for somebody actually in the industry or with an education in this field, it is perfectly clear cut to experts in the field and especially when products release which processes are better than others.

New process generations have become exponentially more expensive to produce. Unless consumers become accepting of exponentially more expensive products, this model can't continue.

Years ago it was said that soon, we will run out of making nodes smaller when transistors became so small it was impossible, like 3 atoms make a transistor and you can't go smaller. Not being an expert here, is that type of thing that we will hit that wall soon ?

As others pointed out, the word game has been going on for some time. The metrics of a process are a better gauge, but still fairly vague in reality.

I think financial limits will stop Moores law long before quantum tunneling.

 

[LightningZ71]

I think the wall is at the limits of EUV/high NA EUV production gear. Anything replacing that will be massively more expensive and so sensitive to any sort of vibration that it's doubtful it could ever repay it's development/purchase costs for anyone involved.

Even using chiplets will only take you so far.

 

[511]

I think the wall is at the limits of EUV/high NA EUV production gear. Anything replacing that will be massively more expensive and so sensitive to any sort of vibration that it's doubtful it could ever repay it's development/purchase costs for anyone involved.

Even using chiplets will only take you so far.

Chiplets will help drive cost down

 

[maddie]

New process generations have become exponentially more expensive to produce. Unless consumers become accepting of exponentially more expensive products, this model can't continue.

As others pointed out, the word game has been going on for some time. The metrics of a process are a better gauge, but still fairly vague in reality.

I think financial limits will stop Moores law long before quantum tunneling.

I think the wall is at the limits of EUV/high NA EUV production gear. Anything replacing that will be massively more expensive and so sensitive to any sort of vibration that it's doubtful it could ever repay it's development/purchase costs for anyone involved.

Even using chiplets will only take you so far.

Anyone seen a discussion of the increased steps needed at the finest element level between Finfet and Ribbonfet?

It appears evident that mask, expose, etch & clean, deposit, will have to be done repeatedly for each ribbon layer versus once for a Finfet design. Costs increases rapidly for the new and future design layouts in addition to the raw node increases.

Am I wrong on this?

 

[maddie]

Chiplets will help drive cost down

No.

Chiplets will reduce the cost increase, not eliminate or reverse it. We're on a one way street for a while.