Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

No.

Chiplets will reduce the cost increase, not eliminate or reverse it. We're on a one way street for a while.

Tbh yes but in the end it will depend on design and packing tech

 

[Meteor Late]

I mean, it's pretty evident AMD and Intel have been doing many things already to drive costs down, like chiplets and smaller cores (Zen 5c / Intel E cores). At some point, you run out of ideas to offset the increasing cost of new processes.

 

[511]

Anyone seen a discussion of the increased steps needed at the finest element level between Finfet and Ribbonfet?

Yeah i have seen few articles referring It will require EUV double patterning for tightest pitches both on 18A and N2 it was i think fred chens tweet

It appears evident that mask, expose, etch & clean, deposit, will have to be done repeatedly for each ribbon layer versus once for a Finfet design. Costs increases rapidly for the new and future design layouts in addition to the raw node increases.

Am I wrong on this?

For BSPDN there is requirement for thermal density as well since the transistor are sandwich in between Power and Signal wires

 

[511]

I mean, it's pretty evident AMD and Intel have been doing many things already to drive costs down, like chiplets and smaller cores (Zen 5c / Intel E cores). At some point, you run out of ideas to offset the increasing cost of new processes.

How about changing your name to Late Meteor Lake

 

[maddie]

Yeah i have seen few articles referring It will require EUV double patterning for tightest pitches both on 18A and N2 it was i think fred chens tweet

For BSPDN there is requirement for thermal density as well since the transistor are sandwich in between Power and Signal wires

Not what I meant. Multi-patterning will be needed for any feature smaller than the minimum native resolution. It matters not if it's Finfet or Ribbonfet.

What I'm saying is that each ribbon layer (example, a 3 ribbon transistor), will need at least as many steps as a Finfet transistor. You will need (3X +) steppings at the highest resolution layer for a 3 "Ribbon" Ribbonfet vs a Finfet transistor.

You can process all of the fins in a Finfet simultaneously, but you can only create 1 "Ribbon" at a time. A macro equivalent, would be 3D printing, multiple passes to create vertical structures, but you can create all of the shared layer ones in 1 pass.

This explains the large increase for N2 from TSMC.

I have not seen this discussed, has anyone?

 

[LightningZ71]

I do think that Strix Point and past mobile devices chips show the future with having a few big performance cores and more numerous fully capable but lighter weight cores.

 

[511]

Not what I meant. Multi-patterning will be needed for any feature smaller than the minimum native resolution. It matters not if it's Finfet or Ribbonfet.

What I'm saying is that each ribbon layer (example, a 3 ribbon transistor), will need at least as many steps as a Finfet transistor. You will need (3X +) steppings at the highest resolution layer for a 3 "Ribbon" Ribbonfet vs a Finfet transistor.

You can process all of the fins in a Finfet simultaneously, but you can only create 1 "Ribbon" at a time. A macro equivalent, would be 3D printing, multiple passes to create vertical structures, but you can create all of the shared layer ones in 1 pass.

This explains the large increase for N2 from TSMC.

I have not seen this discussed, has anyone?

These things should be out by IEDM24

 

[Meteor Late]

I do think that Strix Point and past mobile devices chips show the future with having a few big performance cores and more numerous fully capable but lighter weight cores.

Yeah, one would think the consumer would see the benefit of that in terms of pricing, though, not the prices we are getting for the HX 370 chip.

 

[LightningZ71]

Keep in mind, the HX370 has the equivalent of an updated 6500xt GPU in it on top of a hefty NPU and more cores than any APU from AMD has ever had before etched with a near leading edge process. It's not tiny either.

 

[Thunder 57]

Keep in mind, the HX370 has the equivalent of an updated 6500xt GPU in it on top of a hefty NPU and more cores than any APU from AMD has ever had before etched with a near leading edge process. It's not tiny either.

Has anyone found a use for an NPU yet?

 

[jpiniero]

Has anyone found a use for an NPU yet?

Stonks

 

[coercitiv]

Has anyone found a use for an NPU yet?

Yes, we'll mine crypto with them. 🫠

 

[511]

Has anyone found a use for an NPU yet?

Not a Processing Unit (NPU)

 

[Magio]

Has anyone found a use for an NPU yet?

It's extremely good at wasting valuable die area.

 

[yuri69]

Has anyone found a use for an NPU yet?

We've been waiting for that since Apple A15's release...

 

[OneEng2]

I think the wall is at the limits of EUV/high NA EUV production gear. Anything replacing that will be massively more expensive and so sensitive to any sort of vibration that it's doubtful it could ever repay it's development/purchase costs for anyone involved.

Even using chiplets will only take you so far.

Chiplets / tiles allow you to break up the processor into different parts. Each part being smaller allows more die per wafer and better % yield which helps; however, it isn't free since the chiplets must be bonded together somehow as well.

Regardless, the fact remains that the cost of process changes in increasing exponentially while the advantage of a process change has greatly diminishing returns. The strategy can not continue as a mechanism of product differentiation.

Anyone seen a discussion of the increased steps needed at the finest element level between Finfet and Ribbonfet?

It appears evident that mask, expose, etch & clean, deposit, will have to be done repeatedly for each ribbon layer versus once for a Finfet design. Costs increases rapidly for the new and future design layouts in addition to the raw node increases.

Am I wrong on this?

Nope, not wrong. Not only does the development of a new node cost an increasingly huge amount of money, the cost of performing the process is also getting more expensive each iteration.

 

[511]

Btw High Na effectively reduces your max chip size in half from 26 x 33 mm2 to 26x16.5 mm2
(updated the value previous one were wront)

 

[Doug S]

For BSPDN there is requirement for thermal density as well since the transistor are sandwich in between Power and Signal wires

Silicon isn't all that bad of a thermal conductor - about 40% of copper. I doubt it will make that much difference, since the big hitch in cooling is the interface between the chip and cooler. That's why OEMs will cap it, overclockers will lap it, delid it, and people use fancy TIM containing silver etc. to try to overcome the issues at chip/cooler interface.

I suppose if you were concerned about that you could have a bunch of TSVs not connected to any wiring on the chip (and heavily located in areas where you have lots of transistors with high switch rates) that push through all the way to the cooler facing side of the die where you deposit a final full layer of copper to optimally conduct heat through those TSVs. It would be interesting to see the result but while it may help at the margin I just don't think silicon's thermal conductivity is much of an issue outside of maybe a next gen GPGPU trying to push 2500W though a reticle sized die.

 

[jpiniero]

Btw High Na effectively reduces your max chip size in half from 25 x 33 mm2 to 13.5 x 32 mm2

Which is probably fine, given that the wafers will be so expensive.

 

[Hitman928]

Btw High Na effectively reduces your max chip size in half from 25 x 33 mm2 to 13.5 x 32 mm2

This may not end up being true, there's research suggesting a path that allows for significantly larger reticle sizes with high NA than previously thought.

Silicon isn't all that bad of a thermal conductor - about 40% of copper. I doubt it will make that much difference, since the big hitch in cooling is the interface between the chip and cooler. That's why OEMs will cap it, overclockers will lap it, delid it, and people use fancy TIM containing silver etc. to try to overcome the issues at chip/cooler interface.

I suppose if you were concerned about that you could have a bunch of TSVs not connected to any wiring on the chip (and heavily located in areas where you have lots of transistors with high switch rates) that push through all the way to the cooler facing side of the die where you deposit a final full layer of copper to optimally conduct heat through those TSVs. It would be interesting to see the result but while it may help at the margin I just don't think silicon's thermal conductivity is much of an issue outside of maybe a next gen GPGPU trying to push 2500W though a reticle sized die.

Silicon is a pretty good thermal conductor, the problem is that with BSPD, at least as has been proposed, you are un-flipping the chip so that it's not really silicon between the heat source (FETs) and thermal boundary. Additionally, the silicon must be drastically thinned for the TSVs which means that the heat can't spread properly either. This causes a significant thermal problem for higher power designs. Papers have shown some mitigations for it (e.g., thermal TSVs) but it doesn't really solve the problem, just helps a bit. So far, only Intel has claimed a solution to the issue, but they haven't shared at all how they have accomplished it. I'm guessing that TSMC's BSPD delay and improvement to "super power rail" is in part trying to mitigate the thermal issue and part of that may be that they won't thin the dies quite as much as in the past (which creates potential issues for the TSVs so they'd need a solution for that if they do less thinning).

 

[511]

Intel High NA Adoption - Semiwiki

On Friday April 12th Intel held a press briefing on their adoption of High NA EUV with Intel fellow and director of lithography Mark Phillips. In 1976 Intel built Fab 4 in Oregon, the first Intel fab outside of California. With the introduction of 300mm Oregon became the only development site...

semiwiki.com

A good article for info on High na they will allow stitching to make large die size don't forget Intel has their mask Shop which TSMC also uses

As for heat transfer for BSPDN it is a major consideration and 18A is with and without BSPDN as a feature funnily Intel deflected the question when asked about the heat transfer and capabilities of their Power Via saying they have everything figured out

 

[SiliconFly]

.

 

[511]

Yeah skatterbench said it's the V/F curve that is getting the changes that is quite the news lol

https://twitter.com/x/status/1860847507653456015

 

[igor_kavinski]

Apparently, some "big changes" are coming our way with the upcoming Arrow Lake µcode update.

How are the supposed changes big? Is this going to be a rehash of RPL issue where Intel determines that the CPU can take greater voltage spikes in the short term but long term it gets cooked? Only way it would be "big changes" is if they manage to beat 14900KS gaming scores in every game.

 

[RTX]

Intel High NA Adoption - Semiwiki

On Friday April 12th Intel held a press briefing on their adoption of High NA EUV with Intel fellow and director of lithography Mark Phillips. In 1976 Intel built Fab 4 in Oregon, the first Intel fab outside of California. With the introduction of 300mm Oregon became the only development site...

semiwiki.com

A good article for info on High na they will allow stitching to make large die size don't forget Intel has their mask Shop which TSMC also uses

As for heat transfer for BSPDN it is a major consideration and 18A is with and without BSPDN as a feature funnily Intel deflected the question when asked about the heat transfer and capabilities of their Power Via saying they have everything figured out

Intel's competitors can find out after doing teardowns of PTL/CWF.