Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[9949asd]

First pics : 258V 22W soc power, HX370 15W.

Last pic : 258V 12W soc power, HX370 9W.

So that s just a tiny 50% more power.

Yeah, it crush everything when it comes to cheating.



Same here, 258V at 12W vs 9W for the 370, that s just a joke of a test.

The joke is you, and you need to ask AMD what kind of joke sensor use in there.

Limited board power to 30w, the soc sensor only showing 12w?! Where are the 18w power go??? And the screen power is not included!🤡

 

[SiliconFly]

.

 

[Wolverine2349]

P core to E core ration is roughly 1:3. Also, if not for the massive NPU, we could've almost had 8 more E cores.

Yes for sure. Sick and tired of NPUs and this AI garbage hype.

I hate AI and MS CoPilot being shoved down out throats!!

I will never use such things!!

Terminator and Matrix anyone!! Its scary!!

 

[DavidC1]

By the way, here's the core area numbers on Lunarlake.

Skymont: 1.15mm2, 1.75mm2 with L2
Lion Cove: 3.43mm2 without L2, 4.67mm2 with

@Hitman928 The above is fair bit smaller than the block diagram based shot they gave a while ago. Skymont was 1.3mm2 based on the block diagram shot.

The 3:1 ratio for P vs E still applies. More embarassment for P core team.

 

[cannedlake240]

Please take a look at Lunarlake and tell me there's enough SRAM cells to change density improvements from 60% to 30% just because SRAM doesn't scale as well. Even if we assume SRAM improvement is 0%, it's a big stretch.

Daniel Nenni was guessing and he's wrong.

This is TSMC's own claim lol, by their estimation N3 is 1.3X density over N5 for a monolithic chip. Compare apple A16 to A17 Pro transistor density, it's almost exactly 30% higher, so around 35% higher than the original N5, even though TSMC claims 1.6X logic density increase, while SRAM offers almost no scaling.

 

[controlflow]

Power is stated on the captured screens, and yet he write that it s at 15W despite 22W
being displayed on the screen shots.

They limited the whole system power to 30W and 15W excluding the display.

In the 15W scenario, LNL got an SOC power of ~12W and this includes the DRAM. The AMD chips got 8-9W because there are clearly other things on that board that are eating into the power (including DRAM). AMD was punished in this test for having a less integrated and less efficient overall system design.

You may not like the results but a test like this where power is kept equal at the system level is much more fair than comparing package power when there are differences on what is included in the package.

LNL is simply on a different level in real world low power applications compared to the AMD solutions.

 

[adroc_thurston]

comparing package power

Fair IP comparison.

where power is kept equal at the system level

BOM cheese.

having a less integrated and less efficient overall system design.

Yes costs are a factor you know.

 

[AMDK11]

LNL die shots.

https://twitter.com/x/status/1841497643178148185

This is what I was afraid of. By switching to completely new microarchitectural design methods and tools, Intel has removed artificial boundaries, creating larger logical blocks with more cells, resulting in less visibility of detail, similar to AMD's Zen.

But despite this, you can see that LionCove is a completely new project from scratch.

 

[9949asd]

They limited the whole system power to 30W and 15W excluding the display.

In the 15W scenario, LNL got an SOC power of ~12W and this includes the DRAM. The AMD chips got 8-9W because there are clearly other things on that board that are eating into the power (including DRAM). AMD was punished in this test for having a less integrated and less efficient overall system design.

You may not like the results but a test like this where power is kept equal at the system level is much more fair than comparing package power when there are differences on what is included in the package.

LNL is simply on a different level in real world low power applications compared to the AMD solutions.

The ram or other on board devices will not cost that much of powers. It’s just the sensors problem, better ask amd what kind of sensor they use in there lol

 

[poke01]

This is how battery life tests should be done. Use real world applications that most people use on laptops.

Intel did a great job here and yes some have OLED panels but eh. It’s a true low power chip compared to X Elite and HX 370. That’s why I say Lunar Lakes only competition is M3. This also why most OEMs should ask for a V2 of Lunar Lakes and Intel should continue the V series. Panther Lake will not achieve the same levels of idle power consumption.

 

[KompuKare]

By the way, here's the core area numbers on Lunarlake.

Skymont: 1.15mm2, 1.75mm2 with L2
Lion Cove: 3.43mm2 without L2, 4.67mm2 with

@Hitman928 The above is fair bit smaller than the block diagram based shot they gave a while ago. Skymont was 1.3mm2 based on the block diagram shot.

The 3:1 ratio for P vs E still applies. More embarassment for P core team.

I wonder if once the release is done (and Zen5c) if we then have enough info to get perf/area and perf/transistor for all current cores?

(With different parts of chips scaling differently perf/transistors might be almost impossible without the vendors giving out transistor counts though.)

 

[DavidC1]

I wonder if once the release is done (and Zen5c) if we then have enough info to get perf/area and perf/transistor for all current cores?

(With different parts of chips scaling differently perf/transistors might be almost impossible without the vendors giving out transistor counts though.)

Transistor counts don't really matter because they give wildly differing ones. Performance, performance per watt, peak clocks, performance at certain area, those matter.

 

[adroc_thurston]

Lion Cove: 3.43mm2 without L2, 4.67mm2 with

Oh that's Very Bad for an N3 core.

 

[DavidC1]

Geekerwan says the 8MB MLC latency is 3x the latency of the L3 that is used on the P cores, which seriously limits performance of the E cores, which is why it's named LPE cores, and the latency is generally significantly higher all the way to memory.

The MLC cache is really optimized for power savings by reducing access to memory for all the misc and IO functions which does fit the goal for Lunarlake.

 

[Abwx]

They limited the whole system power to 30W and 15W excluding the display.

In the 15W scenario, LNL got an SOC power of ~12W and this includes the DRAM. The AMD chips got 8-9W because there are clearly other things on that board that are eating into the power (including DRAM). AMD was punished in this test for having a less integrated and less efficient overall system design.

You may not like the results but a test like this where power is kept equal at the system level is much more fair than comparing package power when there are differences on what is included in the package.

LNL is simply on a different level in real world low power applications compared to the AMD solutions.

Whatever they did it s displayed 22W SoC power for the 258V while it s 15W SoC power for the 370, SoC power is what is used by the chip, dunno what you are trying to justify here, numbers are numbers.

At 12W the 258V is faced by a 370 at 9W, also SoC powers...

 

[9949asd]

ARL will be really good at performance and power consumption.

 

[DavidC1]

Whatever they did it s displayed 22W SoC power for the 258V while it s 15W SoC power for the 370, SoC power is what is used by the chip, dunno what you are trying to justify here, numbers are numbers.

Which means Lunarlake is efficient at the system level that they can juice more to the SoC yet offer same battery life, ending up as a superior product. Geekerwan also got his numbers using handhelds for the Ryzen meaning if anything it should have system level advantage.

In a handheld, that means 22W Lunarlake gets the same battery life as a 15W HX 370 while offering far greater performance.

Or just like @9949asd says AMD's sensors are bonked and is showing artificially low numbers.

 

[cannedlake240]

ARL will be really good at performance and power consumption.
View attachment 108576

Can x86 cores at least catch up to M3 what is this

 

[poke01]

Can x86 cores at least catch up to M3 what is this

desktop x86 CPUs absolutely. You see the reason why the M chips have such high ST is because Apple wanted to make an all purpose core that can used in mobile and desktop without sacrificing ST for mobile. If you go with that foundation for building chips you get the M series.

 

[Abwx]

The joke is you, and you need to ask AMD what kind of joke sensor use in there.

Limited board power to 30w, the soc sensor only showing 12w?! Where are the 18w power go??? And the screen power is not included!🤡

They go nowhere, this review is just dubbious, if the 370 plateform would need 30W to feed the Soc with 12W then the 370 coudnt score17k at 30W in R23 while the 288V is stuck at 10k at this same power.

Just go watch the video fanboy, the total power will not lie, but the software numbers will!

The fanboy is the one who is shawn 22W in a screen and is still claming that it s 15W,

Look better your own screenshots, 10% higher fps at 50% more power :

 

[511]

Is this SoC Power same as Package Power reading from HwInfo?

 

[DavidC1]

They go nowhere, this review is just dubbious, if the 370 plateform would need 30W to feed the Soc with 12W then the 370 coudnt score17k at 30W in R23 while the 288V is stuck at 10k at this same power.


The fanboy is the one who is shawn 22W in a screen and is still claming that it s 15W,

Look better your own screenshots, 10% higher fps at 50% more power :

So what? He's measuring motherboard power, so either AMD's system is a) wasting more system power thus can't allocate much to SoC or b) AMD's sensors are bonked and it's using close to 20W rather than 15W. If Geekerwan adjusted it so they all use same SoC power than Lunarlake system will use quite bit lower system power and thus achieve better gaming battery life.

So you have a much better handheld on Lunarlake, because you either get much better performance at the same battery life, or noticeably better battery life at similar performance.

 

[511]

Can x86 cores at least catch up to M3 what is this

Zen 6 40% and Nova Lake 40% Cope ?

 

[Magio]

The fanboy is the one who is shawn 22W in a screen and is still claming that it s 15W,

You're looking at the 30W board power chart. It's literally on the picture you reposted. Geekerwan did both 15W and 30W board power tests and LNL came out on top in both.

 

[DavidC1]

You're looking at the 30W board power chart. It's literally on the picture you reposted. Geekerwan did both 15W and 30W board power tests and LNL came out on top in both.

You can see on the AMD's side, Steam Deck is most efficient with system capped at 15W, so Valve made a good choice.