Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[H433x0n]

That s wrong, for the S16 Computerbase measured 28W in CB in HVinfo and NBC measured a little more than 30W for CB at the main, so AMD s telemetry is very accurate and it so for many years, beside you re talking of the Z1ex, dunno what it has to do with the 370.

All numbers for 288V and 370 can be found here :

Intel Core Ultra 9 288V „Lunar Lake“ im Test

Es ist so weit: Nach einem Jahr Salamischeibenmarketing ist Intel Lunar Lake ab sofort verfügbar. Core Ultra 200V überzeugt im Test.

www.computerbase.de

Where does it say they are measuring power draw in a similar fashion as Geekerwan? I read the translated text and I do not see it.

 

[SiliconFly]

.

 

[Abwx]

Where does it say they are measuring power draw in a similar fashion as Geekerwan? I read the translated text and I do not see it.

Go at NBC they have scores of power measurements at the main, i linked an article,
difference is that i read all articles be it about AMD or Intel while here there s apparenly lot of people who only rely on earsay when it comes to AMD, hence the lengthy and useless debate because there s homewoks that are not done.

 

[511]

Therefore history doesn't repeat but rhymes. It is mini Netburst to Core all over again. Raptorlake degradation is Pentium III 1.13GHz but 23 years later. The motivation is quite similar. Both pushed clocks too high to better go against competition, which in both cases is AMD.

It was not really the clocks but a combination of different things all happening at once
>eTVB
>MOBO maker defaults
>Core requesting Insane VIDs
> Bug in clock circuitry
But ut will hamper future sale at least Intel 7 is a depreciated Node so everything now only cost them the amount to make it they can literally sell i9 for $250-300 and make a profit

 

[AMDK11]

 

[SiliconFly]

.

 

[AMDK11]

Are you sure it's a new design? I'm under the impression, LNC is basically a port of RWC from in-house design tools to industry standard design tools while being modular & agnostic (portable). Meaning, it's basically RWC with some decent core upgrades but on a solid foundation that'll help them immensely going forward. Am I correct? If yes, I'm expecting some decent uplift starting cougar cove itself.

LionCove is a fundamentally new project and has little in common with RedwoodCove. The change from the unified FP-ALU schedule and the separation of FP into a separate block and ALU into a separate one makes this a fundamental change. I believe that LionCove is the beginning of major changes in P-Core. Time will verify whether I was right.

 

[Jan Olšan]

It was not really the clocks but a combination of different things all happening at once
>eTVB
>MOBO maker defaults

Pretty sure those were defaults that the motherboard makers used more or less under Intel's influence, because Intel was who benefited.
After all, you only have to look at AM4 and AM5 where specs are specs and this thing doesn't exist. And also, remember how quickly Intel cracked down on overclocking of non-K CPUs.
Intel always had the power to stop this instantly but they didn't, which clearly shows the "4095W" way was how Intel wanted it.

>Core requesting Insane VIDs
> Bug in clock circuitry

No! The clock tree was simply the first of the circuits that would fail/show damage from the generally dangerous voltage. That is not a bug and you can't really blame the poor transistors from dying due to mistakes being made elsewhere.

But ut will hamper future sale at least Intel 7 is a depreciated Node so everything now only cost them the amount to make it they can literally sell i9 for $250-300 and make a profit

 

[Hitman928]

By the way, here's the core area numbers on Lunarlake.

Skymont: 1.15mm2, 1.75mm2 with L2
Lion Cove: 3.43mm2 without L2, 4.67mm2 with

@Hitman928 The above is fair bit smaller than the block diagram based shot they gave a while ago. Skymont was 1.3mm2 based on the block diagram shot.

The 3:1 ratio for P vs E still applies. More embarassment for P core team.

I’m on vacation right now but will take a look when I get back.

 

[511]

Pretty sure those were defaults that the motherboard makers used more or less under Intel's influence, because Intel was who benefited.
After all, you only have to look at AM4 and AM5 where specs are specs and this thing doesn't exist. And also, remember how quickly Intel cracked down on overclocking of non-K CPUs.
Intel always had the power to stop this instantly but they didn't, which clearly shows the "4095W" way was how Intel wanted it.

Oh yeah i agree they should have Stopped the nonsense it Lives on Laptops as well look at MTL/RPL-H with 115W that's nonsense 80W should be the max really

No! The clock tree was simply the first of the circuits that would fail/show damage from the generally dangerous voltage. That is not a bug and you can't really blame the poor transistors from dying due to mistakes being made elsewhere.

I don't know exactly what it means tbh but it is a Design flaw nonetheless do we not call it a bug ?

 

[9949asd]

Pretty sure those were defaults that the motherboard makers used more or less under Intel's influence, because Intel was who benefited.
After all, you only have to look at AM4 and AM5 where specs are specs and this thing doesn't exist. And also, remember how quickly Intel cracked down on overclocking of non-K CPUs.
Intel always had the power to stop this instantly but they didn't, which clearly shows the "4095W" way was how Intel wanted it.

No! The clock tree was simply the first of the circuits that would fail/show damage from the generally dangerous voltage. That is not a bug and you can't really blame the poor transistors from dying due to mistakes being made elsewhere.

Pretty sure those were defaults that the motherboard makers used more or less under Intel's influence, because Intel was who benefited.
After all, you only have to look at AM4 and AM5 where specs are specs and this thing doesn't exist. And also, remember how quickly Intel cracked down on overclocking of non-K CPUs.
Intel always had the power to stop this instantly but they didn't, which clearly shows the "4095W" way was how Intel wanted it.

No! The clock tree was simply the first of the circuits that would fail/show damage from the generally dangerous voltage. That is not a bug and you can't really blame the poor transistors from dying due to mistakes being made elsewhere.

It’s mother board company who want to show the difference performance on their MB, then come out with “default “ enabled 4096w 512A limit. This happened like almost 10years, but intel didn’t stop it.
Good news is z890 b860 will force to use intel default setting when out of box.

 

[511]

Easy Anti Cheat isn't playing nice with Windows 11 24H2, but happily you SHOULDN'T be affected by it — here's why

EAC and the latest version of Windows 11 aren't playing nice on some systems, but those affected shouldn't be getting the update right now.

www.windowscentral.com

I can't believe this left out of testing imagine not testing windows on things that will run on it especially Kernel Anti Cheat after Crowd strike

 

[CouncilorIrissa]

Can you send here? Twitter is dead in brazil

There you go.

 

[Doug S]

I wonder if once the release is done (and Zen5c) if we then have enough info to get perf/area and perf/transistor for all current cores?

(With different parts of chips scaling differently perf/transistors might be almost impossible without the vendors giving out transistor counts though.)

David Kanter explains it better than I or most anyone else ever could:

https://www.realworldtech.com/transistor-count-flawed-metric/

 

[Saylick]

Can you send here? Twitter is dead in brazil

Here you go:

 

[cannedlake240]

LionCove is a fundamentally new project and has little in common with RedwoodCove. The change from the unified FP-ALU schedule and the separation of FP into a separate block and ALU into a separate one makes this a fundamental change. I believe that LionCove is the beginning of major changes in P-Core. Time will verify whether I was right.

Nah, this is a misconception likely originating from MLID, about Lioncove bring a part of royal core/an entirely new project and uarch team led by Jim Keller. That's simply not true. Lioncove still has a lot in common with redwood cove and all prior Intel core uarch as shown by C&C and David Huang's articles. The core still behaves largely the same in a lot of key metrics

 

[mvprod123]

I remember reading most of the top talent in the Apple silicon team have left leaving the rest to just iterate. Probably one of the reasons M series silicon hasn't had any major performance/efficiency jumps lately.

The results of the Oryon core showed that the role of people who left Apple was exaggerated, Apple did not lose its leadership in IPC during these 4 years.

A M3 P core vs LNL P core direct comparison should shed more light on area-efficiency, overall-efficiency, performance (per transistor or area or whatever the unit is), etc. It's gonna be very interesting. Will show how behind Intel P core team is.

I couldn't find the size of the M3 P-core, but instead found the size of the M2 P-core. The Lunar Lake P-core roughly matches the performance of the M2 P-core.

Apple M2 Die Shot and Architecture Analysis – Big Cost Increase And A15 Based IP

Apple announced their new 20 billion transistor M2 SoC at WWDC. Unfortunately, it’s quite a minor uplift in performance in some areas such as CPU. Apple’s gains mostly came from the GPU and video editing side of things.

www.semianalysis.com

 

[Jan Olšan]

Oh yeah i agree they should have Stopped the nonsense it Lives on Laptops as well look at MTL/RPL-H with 115W that's nonsense 80W should be the max really

I don't know exactly what it means tbh but it is a Design flaw nonetheless do we not call it a bug ?

Let me rephrase it: inevitably, something will break in the processor if you feed it excessive voltage. It just happened to be the clock tree. It's likely that the next-in-the-line to failing circuitry doesn't have much better voltage tolerance. Clock tree is also a permanently stressed element, so it gets voltage-fried more often than some other parts.

It's quite possible it was carried over from Alder Lake. You could say it was flawed if it was supposed to only get damaged at 1.6V and it already gave up 1.55V, but I expect it wasn't really like that, the circuitry likely just got more voltage than it was designed to safely handle (blame: the whole voltage control system).

It’s mother board company who want to show the difference performance on their MB, then come out with “default “ enabled 4096w 512A limit. This happened like almost 10years, but intel didn’t stop it.
Good news is z890 b860 will force to use intel default setting when out of box.

How can motherboard vendors show a difference when all of them do this? They just ended up being on square one again, so I don't see this as being true.
You could say that it allows them to show a difference between their own lowly H610 board and another pricy Z790 board. But in that case, why didn't they ask AMD to get them similar ability on AM4 and AM5 platform?

 

[H433x0n]

Go at NBC they have scores of power measurements at the main, i linked an article,
difference is that i read all articles be it about AMD or Intel while here there s apparenly lot of people who only rely on earsay when it comes to AMD, hence the lengthy and useless debate because there s homewoks that are not done.

I’ll just ask it outright, do you believe it’s possible that Lunar Lake could be a better low power SoC than Strix?

I’m getting the sense that the only results you will consider valid are the ones that would show Strix as being more efficient.

 

[9949asd]

Let me rephrase it: inevitably, something will break in the processor if you feed it excessive voltage. It just happened to be the clock tree. It's likely that the next-in-the-line to failing circuitry doesn't have much better voltage tolerance. Clock tree is also a permanently stressed element, so it gets voltage-fried more often than some other parts.

It's quite possible it was carried over from Alder Lake. You could say it was flawed if it was supposed to only get damaged at 1.6V and it already gave up 1.55V, but I expect it wasn't really like that, the circuitry likely just got more voltage than it was designed to safely handle (blame: the whole voltage control system).


How can motherboard vendors show a difference when all of them do this? They just ended up being on square one again, so I don't see this as being true.
You could say that it allows them to show a difference between their own lowly H610 board and another pricy Z790 board. But in that case, why didn't they ask AMD to get them similar ability on AM4 and AM5 platform?

Because after the first one does it, everyone must follow up. Unlock the power limit happened at 4770k to 4790k. Unlock power limit can boost up 5 to 10% performance.

About amd motherboard, they did it too. Remember when 7800x3d 7950x3d just came out there were some cpu burned? Venders was overvoltages it, but amd quickly force them to change bios.

 

[poke01]

I’ll just ask it outright, do you believe it’s possible that Lunar Lake could be a better low power SoC than Strix?

I’m getting the sense that the only results you will consider valid are the ones that would show Strix as being more efficient.

It’s impossible for Strix point to be lower power than Lunar lake, even next gen Zen6 APU won’t reach Lunar levels if AMD doesn’t follow the design of Lunar.

 

[adroc_thurston]

if AMD doesn’t follow the design of Lunar.

There are other hacks to get lower power.
But they're also $$$.
PTL and NVL mobile both focus on trimming down the excess in the name of more palatable BOM, and for a good reason.

 

[poke01]

There are other hacks to get lower power.
But they're also $$$.
PTL and NVL mobile both focus on trimming down the excess in the name of more palatable BOM, and for a good reason.

Now NVL might have a chance? Isn’t that Arctic Wolf for e core. Something tells me that core might be cool

 

[DavidC1]

I’m on vacation right now but will take a look when I get back.

I looked at the block diagram shot again. I had suspicions that it wouldn't be 100% accurate because it wasn't an actual die shot.

With the block diagram shot I'm getting 1.3-1.35mm and 4.4mm for P and E, w/o L2 on E and w/L2 on P. It isn't the P core size that got smaller, the E core did though. The actual die shot I'm getting 1.14-1.15mm2 w/o L2 and 1.75mm2 with L2.

 

[H433x0n]

There are other hacks to get lower power.
But they're also $$$.
PTL and NVL mobile both focus on trimming down the excess in the name of more palatable BOM, and for a good reason.

Eh, the costs are worth it and required to compete at the highest level.

I think it’d be in best interest of Intel to create a new product segment based off of LNL. Client is now their main revenue stream, hanging onto it should be among its top priorities. To kill off a successful product segment for BOM optimization is a mistake. If LNL is a sales success, they could charge more to offset the higher costs.