Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Wolverine2349]

They’d have to go to a mesh interconnect which has significant power and latency consequences.

If they were all P cores say 12 of them, could Intel reliable get them on a singhle ring bus with no clusters like they did 10 on 10900K/10850K with good stability and latency.

Or is it too hard to get more than 8-10 of any core type on a ring bus with good stability. Thus why the e-cores are in 4 core clusters? Or is it because they are a different core type they need to be in clusters but if they were homogenous core type they could fit 12 or maybe 16 P cores reliably on a ring bus without them being in 4 core clusters?

 

[Hitman928]

If they were all P cores say 12 of them, could Intel reliable get them on a singhle ring bus with no clusters like they did 10 on 10900K/10850K with good stability and latency.

Or is it too hard to get more than 8-10 of any core type on a ring bus with good stability. Thus why the e-cores are in 4 core clusters? Or is it because they are a different core type they need to be in clusters but if they were homogenous core type they could fit 12 or maybe 16 P cores reliably on a ring bus without them being in 4 core clusters?

Going from memory, around 10 - 12 nodes seems to be the max Intel can really get on a single ring. Anything more than that will need either a dual ring design or full on mesh if you get to many cores. I'd have to look up past designs and commentary on it to be sure, but I don't really have the time/motivation to do so.

 

[511]

Certainly not in nT.
13100F(4P+0E, 58W TDP -> 75W in Prime95) managed only 8844 points in CB R23.
i7-1365U(2P+8E, 28W sustained) 9576 points in CB R23.
So higher score at 1/2 TDP or less.
These E-cores despite their disadvantages are not just for show.

I meant for area comparison 4 ecores = 1.2-1.3X P cores but yeah E cores are not meme cores people have been saying Chadmont will just show us the power ⚡

 

[DavidC1]

If they were all P cores say 12 of them, could Intel reliable get them on a singhle ring bus with no clusters like they did 10 on 10900K/10850K with good stability and latency.

They probably can. The cluster approach saves area, and they can easily port it among different segments such as laptops, servers, and desktops.

Needing only one ring stop would be one reason they use it on the desktop version.

Not having a dedicated high performance version is likely just to prevent cannabilization between segments plus avoiding extra cost on a new SoC.

Certainly not in nT.
13100F(4P+0E, 58W TDP -> 75W in Prime95) managed only 8844 points in CB R23.
i7-1365U(2P+8E, 28W sustained) 9576 points in CB R23.
So higher score at 1/2 TDP or less.
These E-cores despite their disadvantages are not just for show.

Desktop vs Laptop CPUs aren't the same though. The few % differences in internal firmware, memory latency, binning, idle power differences will all add up, plus motherboard settings which might increase peak power significantly for few % faster performance.

 

[Wolverine2349]

Going from memory, around 10 - 12 nodes seems to be the max Intel can really get on a single ring. Anything more than that will need either a dual ring design or full on mesh if you get to many cores. I'd have to look up past designs and commentary on it to be sure, but I don't really have the time/motivation to do so.

Yeah that makes sense. And 10-12 nodes. Does a 4 e-core cluster count as 1 node? Thus Intel has 16 e-cores on Arrow Lake and Raptor Lake because they have 8 P cores and each e-core is a 4 core cluster as once node so thus 12 total nodes?

 

[Wolverine2349]

They probably can. The cluster approach saves area, and they can easily port it among different segments such as laptops, servers, and desktops.

Needing only one ring stop would be one reason they use it on the desktop version.

Not having a dedicated high performance version is likely just to prevent cannabilization between segments plus avoiding extra cost on a new SoC.

Desktop vs Laptop CPUs aren't the same though. The few % differences in internal firmware, memory latency, binning, idle power differences will all add up, plus motherboard settings which might increase peak power significantly for few % faster performance.

Yes and I really hope Intel makes 12 Lion Cove cores of Arrow Lake. I would buy ina heartbeat. Could run WIN10 or 11, no Process Lasso, excellent RAM overclocking lower power than rumored 12 + 0 Bartlett Lake and 2 dedicated X4 NVME lanes to CPU.

I am praying and hoping maybe it surprisingly shows up at launch as maybe the Core Ultra 286K or 295K?? or maybe 285KG woith G being for gaming

Probably not but I really hope.

Intel could really put a dent in AMD if they did such a thing especially with Zen 5 underwhelming flop. Lots of people are not fond of dual CCD and especially the worse scheduling issue flop and Big.Little.

Though Intel financial situation would probably make it harder, but Intel is big and mighty Intel and they laid of employees to cut costs so they are still fine. Plus 10nm process node costs more than their 20A and TSMC so they could do 12 P core Arrow Lake die in addition to the 8 +16 hybrid die cheaper than 12 P core plus 8 + 16 Bartlett/Raptor Lake.

 

[Hitman928]

Yeah that makes sense. And 10-12 nodes. Does a 4 e-core cluster count as 1 node? Thus Intel has 16 e-cores on Arrow Lake and Raptor Lake because they have 8 P cores and each e-core is a 4 core cluster as once node so thus 12 total nodes?

Yes.

 

[dullard]

Yes and I really hope Intel makes 12 Lion Cove cores of Arrow Lake. I would buy ina heartbeat. Could run WIN10 or 11, no Process Lasso, excellent RAM overclocking lower power than rumored 12 + 0 Bartlett Lake and 2 dedicated X4 NVME lanes to CPU.

The number of commonly used software that uses more than 8 cores, but fewer than 13 cores is what? None? Close to none? Maybe a specialized game if you crank up the complexity just right?

Your hypothetical chip will do very well if you can find software that needs 10 or 12 cores. No less or no more. But it would mostly be a hammer looking for a nail. If it needs 8 or fewer cores, then 8 powerful P cores is better than 12 weaker P cores. If it needs 13 or more cores, then 8+8 or the rumored 8+16 will destroy that 12 P core CPU.

What you fail to think about is how having 12 P cores makes each P core much slower. Much longer latency with such a long ring. An imaginary 12 strong P core chip just doesn't fit with Intel's designs.

 

[Thunder 57]

The number of commonly used software that uses more than 8 cores, but fewer than 13 cores is what? None? Close to none? Maybe a specialized game if you crank up the complexity just right?

Your hypothetical chip will do very well if you can find software that needs 10 or 12 cores. No less or no more. But it would mostly be a hammer looking for a nail. If it needs 8 or fewer cores, then 8 powerful P cores is better than 12 weaker P cores. If it needs 13 or more cores, then 8+8 or the rumored 8+16 will destroy that 12 P core CPU.

What you fail to think about is how having 12 P cores makes each P core much slower. Much longer latency with such a long ring. An imaginary 12 strong P core chip just doesn't fit with Intel's designs.

Thank you for explaining it better than I could've. There's just no market for something like that.

 

[SiliconFly]

-

 

[Wolverine2349]

The number of commonly used software that uses more than 8 cores, but fewer than 13 cores is what? None? Close to none? Maybe a specialized game if you crank up the complexity just right?

Your hypothetical chip will do very well if you can find software that needs 10 or 12 cores. No less or no more. But it would mostly be a hammer looking for a nail. If it needs 8 or fewer cores, then 8 powerful P cores is better than 12 weaker P cores. If it needs 13 or more cores, then 8+8 or the rumored 8+16 will destroy that 12 P core CPU.

What you fail to think about is how having 12 P cores makes each P core much slower. Much longer latency with such a long ring. An imaginary 12 strong P core chip just doesn't fit with Intel's designs.

There are lots of software namely games that benefit from more than 8 cores buy fewer than 13.

Cyberpunk TLOU PART 1, Stanfield, star Citizen, Spiderman Resmastered, Dragons Dogma 2.

12 p cores no need for cross latency penalty and no big.little scheduling quirks.

Intel had it with Comet Lake.

I hope they make it with Arrow Lake. But does not appear so at least not initially this Fall.

 

[Thunder 57]

There are lots of software namely games that benefit from more than 8 cores buy fewer than 13.

Cyberpunk TLOU PART 1, Stanfield, star Citizen, Spiderman Resmastered, Dragons Dogma 2.

12 p cores no need for cross latency penalty and no big.little scheduling quirks.

Intel had it with Comet Lake.

I hope they make it with Arrow Lake. But does not appear so at least not initially this Fall.

Aren't you making dullard's point? If it made such a vast difference as you seem to suggest it would, you would probably be running a 10 core Comet Lake. Instead, 8 faster P cores perform better.

 

[AcrosTinus]

AnandTech gaming benchmarks. An absolute bloodbath. At this rate, ARL is gonna run circles around the competition without breaking a sweat.

People are sleeping on ARL. Intel has from my perspective a quite simple task of using less power and delivering maybe 5 to 10% more client performance, meaning general purpose performance.
I don't know how big the tile latency penalty will be on desktop but it will be way lower than Zen due to the active substrate.

My crystal ball is telling me 7% better gaming and unleashed 10%.

 

[DavidC1]

What you fail to think about is how having 12 P cores makes each P core much slower. Much longer latency with such a long ring. An imaginary 12 strong P core chip just doesn't fit with Intel's designs.

The "much longer latency" only applied with server chips that needed dual ring stops because it had to hand off data from one side to the other. 12 single ring(or dual bi-directional ones) won't have a big latency hit. The thing is, the single ring only stops at maximum 12 or so.

AnandTech gaming benchmarks. An absolute bloodbath. At this rate, ARL is gonna run circles around the competition without breaking a sweat.

Lol. Next week you are going to call doom and gloom for Arrowlake aren't you?

I don't know how big the tile latency penalty will be on desktop but it will be way lower than Zen due to the active substrate.

You do know Zen 5 has seemingly exactly the same IO die and configuration but increased cross-CCD latencies significantly?

Implementation>>>High level details

Don't judge there will be a tile penalty yet. I think it'll either be very little, or even nonexistent. Meteorlake is a mobile part with significantly higher memory latencies, much conservative clock speed ramp, much slower waking from sleep and other unknowns.

I'll give you another example of implementation being king. Lakefield had a 3D stacked Foveros die meaning it should have been super low latency for high performance, and super low power.

Yet it was slow as molasses in both ST and MT. Jasperlake, the dedicated E core low cost/low power platform using the same Tremont core as the E cores in Lakefield outperformed it in ST, despite LKF having the Sunny Cove P core. And the battery life was no better than previous generation -Y chips.

 

[Wolverine2349]

Aren't you making dullard's point? If it made such a vast difference as you seem to suggest it would, you would probably be running a 10 core Comet Lake. Instead, 8 faster P cores perform better.

It makes a difference and it will grow.

10 p core comet lake please. IPC is so far inferior and behind even Zen 3 and stuck at PCIe Gen 3 lol.

But the gaming market unfortunately too small for intel to care or care about those big.little scheduling quirks.

I wish they had a 12 p core ARL coming but doubtful certainly not right away if ever. It is what it is.

 

[DavidC1]

It makes a difference and it will grow.

10 p core comet lake please. IPC is so far inferior and behind even Zen 3 and stuck at PCIe Gen 3 lol.

But the gaming market unfortunately too small for intel to care or care about those big.little scheduling quirks.

I wish they had a 12 p core ARL coming but doubtful certainly not right away if ever. It is what it is.

They are consolidating things that I think they shouldn't consolidate.* You should expect their finances to drastically improve before they even think of what they are doing. They cancelled Innovation event, which in terms of absolute cost is probably minimal. Few million dollars? Really?

New die and stepping will cost few hundred million dollars.

*Falcon Shores hybrid CPU/GPU cancellation was a stupid idea. AMD's MI300 made $1 billion a quarter in it's first year. The single product makes more money than Intel's many previous huge acquisitions did.

 

[DavidC1]

Rogue River, yes. That's a nice surprise if so. RR should employ Artic Wolf E Cores.

Good.

Regarding this, I think Intel regularly flushes "moles" out.

This means Exist50 is wrong on this. I've seen it repeated many times. They get a reliable leaker, and they are:
a) hired
b) discredited
c) wrong significant amount of the time

b) is what's happening now. Ashraf Eassa was another leaker, he was here in AT forums too. And a) was what happened to him. Intel "snapped" him up, that's all we know.

Guys like MLID, RGT, Adored is not reliable enough for people to trust. When you have real sources then you are right 100% of the time. It only takes 1 wrong info to start discrediting them.

 

[Wolverine2349]

They are consolidating things that I think they shouldn't consolidate.* You should expect their finances to drastically improve before they even think of what they are doing. They cancelled Innovation event, which in terms of absolute cost is probably minimal. Few million dollars? Really?

New die and stepping will cost few hundred million dollars.

*Falcon Shores hybrid CPU/GPU cancellation was a stupid idea. AMD's MI300 made $1 billion a quarter in it's first year. The single product makes more money than Intel's many previous huge acquisitions did.

Which things are they consolidating that they should not in your opinion?

And yeah their financial situation does need to improve for any hope for them to do the product I would like.

 

[LightningZ71]

Any idea if Bartlett lake will have avx-512 enabled since its all p cores?

 

[511]

People are sleeping on ARL. Intel has from my perspective a quite simple task of using less power and delivering maybe 5 to 10% more client performance, meaning general purpose performance.
I don't know how big the tile latency penalty will be on desktop but it will be way lower than Zen due to the active substrate.

My crystal ball is telling me 7% better gaming and unleashed 10%.

The substrate is passive interposer

 

[511]

Any idea if Bartlett lake will have avx-512 enabled since its all p cores?

It is for NEX but they should enable it and people will buy it easily that one VP who pushed thed Idea of Disabling AVX-512 needs to get laid off we were fine with Only P core AVX-512 and the decision needs to be reversed

 

[SiliconFly]

-

 

[Wolverine2349]

ARL's interposer sits on top of a substrate.


ARL is using a newer interconnect fabric that should address the issues (like high latency) with the one in MTL. Btw, ARL is tiles-over-interposer-over-substrate compared to Zen's much older chiplet-over-substrate design. And the interposer is passive in ARL. CWF is the first one to get an active interposer (with adm cache).


After years of lagging behind competition, they now have a good opportunity. Lets hope they don't squander it.


With great power comes great responsibility!


I think bartlett lake isn't for general consumers (not sure).

Is 12 p cores on a ring bartlett lake coming or just a rumor? I really want it if true. The new stepping should hopefully fix degradation and stability issues.

Even 2025 release it should age well given Zen 5 underwhelming uplift and Arrow Lake better but still clock regressed design.

And it's more than 8 cores modern IPC on a single node. Yes I want it if true!

 

[SiliconFly]

-

 

[Henry swagger]

ARL's interposer sits on top of a substrate.


ARL is using a newer interconnect fabric that should address the issues (like high latency) with the one in MTL. Btw, ARL is tiles-over-interposer-over-substrate compared to Zen's much older chiplet-over-substrate design. And the interposer is passive in ARL. CWF is the first one to get an active interposer (with adm cache).


After years of lagging behind competition, they now have a good opportunity. Lets hope they don't squander it.


With great power comes great responsibility!


I think bartlett lake isn't for general consumers (not sure).

Arrow lake performance will be very big.. intel has veen good at hiding its true performance