Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[invisible_city]

Where are you getting that from? It's talking about an SLC, not the regular ring-connected distributed L3.

If you look in the top left corner of the slide, the subtitle says Ring/LLC

 

[Wolverine2349]

The atom core is good. But some Intel users might anyway decide to shut them down to gain better P core OC and compatibility in some situation.

And if you care atom core enough, you should have known E core IPC is already quite good, compare Gracemont to Goldencove is just 16% lower on INT, and 38% lower on FP due to less FPU resources.

Guess why Intel compare Skymont to LP Crestmont in Meteorlake which lacks L3 cache.

View attachment 100431

Yes will be the thing to do if they have a more than 8 P cores on any model in single tile. Otherwise, a waste to do so and just get 9700X or 9800X3D for only 8 cores of similar performance. Unless you just love Intel and are ok with losing SMT with only 8 cores.

 

[csbin]

Great article.

Comparing Crestmonts: No L3 Hurts

Meteor Lake’s standard E-Cores share a 24 MB L3 cache with the P-Cores, while the LPE-Cores have to make do with just their private 2 MB L2. Caching is critical to performance in modern CPUs …

chipsandcheese.com

 

[DavidC1]

Gracemont is around skylake IPC. Skymont is around Raptor Cove IPC, which is a jump of around 20-50% (specint int 20%, fp 50%) AND gets a clock boost.

What are you smoking? Sunny Cove is 18% faster than Skylake and Golden Cove is 19% faster than Sunny.

Skymont is 38% faster than Gracemont. This is a blowout increase alone, but there's also a 68% FP increase coming from the straight up doubling of FP performance, which will benefit vast majority of applications from beginning of the FP era, without needing to recompile like AVX512.

Skymont's FP unit is more capable than Golden Cove in
-64-bit FP: Literally everything
-128-bit FP: Everything from Core 2
-256-bit FP: Somewhat worse.

Assuming Int/FP split of 65/35%, that's a 50% gain. In 2022 it was Raptor Lake with Gracemont, and Golden Cove enhanced, and Zen 4.

 

[jpiniero]

Intel Xeon 6780E / Xeon 6766E 144-Core Performance Benchmarks Review - Phoronix

www.phoronix.com

Phoronix has a review of Sierra Forrest. It doesn't do so hot on the benchmarks that use AVX-512 obviously but it does manage to do reasonably okay in most of them. And the PPW is much better than Emerald Rapids.

 

[Henry swagger]

What are you smoking? Sunny Cove is 18% faster than Skylake and Golden Cove is 19% faster than Sunny.

Skymont is 38% faster than Gracemont. This is a blowout increase alone, but there's also a 68% FP increase coming from the straight up doubling of FP performance, which will benefit vast majority of applications from beginning of the FP era, without needing to recompile like AVX512.

Skymont's FP unit is more capable than Golden Cove in
-64-bit FP: Literally everything
-128-bit FP: Everything from Core 2
-256-bit FP: Somewhat worse.

Assuming Int/FP split of 65/35%, that's a 50% gain. In 2022 it was Raptor Lake with Gracemont, and Golden Cove enhanced, and Zen 4.

In two years,
-P core Intel got 14% gain
-P core AMD got 16% gain
-E core Intel got 50% gain

Three years of 14%: 48%
Three years of 16%: 56%

Conclusion 1: Three times two year gains of P cores delivered in 2 years. Feast on that. I had a good feeling the E core team will make a breakout someday.
Conclulsion 2: 50% is Bulldozer to Zen level gains. Unlike Bulldozer though Gracemont was pretty good already.

Where is intel's e team based at ?

 

[Hitman928]

Where is intel's e team based at ?

Oregon IIRC.

 

[DavidC1]

In two years,
-P core Intel got 14% gains
-P core AMD got 16% gains
-E core Intel got 50% gains

Three years of 14%: 48%
Three years of 16%: 56%

Skylake was late 2015. So it took the Intel P core team 9 years to deliver 60% gains. E core team did it in two.

Conclusion 1: Three times two year gains of P cores delivered in 2 years. Feast on that. I had a good feeling the E core team will make a breakout someday.
Conclulsion 2: 50% is Bulldozer to Zen level gains. Unlike Bulldozer though Gracemont was pretty good already.

 

[Saylick]

You can't read the slides either

The vs raptor cove is not Lunar Lake LP Skymont vs Raptor Cove, but an undisclosed (Arrow Lake) implementation where the Skymont cluster is on the ring bus (and shares L3 with P-cores)

Username checks out.

Point is, Intel is using a L3 cache for these Skymont comparisons.

 

[gdansk]

So in Lunar Lake the cache structure for the P core is as follows:
L1 (48K),
L2 (192K),
L3 (2.5MB),
L4 (12MB),
L5 (8MB)

Is that right?

 

[DavidC1]

Yes.

But it isn't L5. The system level cache is mostly for power saving purposes by reducing distance of data access ala Apple Mx chips. The performance advantage of the system level cache won't be as significant as having L3 cache.

 

[gdansk]

Yes.

But it isn't L5. The system level cache is mostly for power saving purposes by reducing distance of data access ala Apple Mx chips. The performance advantage of the system level cache won't be as significant as having L3 cache.

It can still access it though? Why is the nomenclature L# is not applicable.

 

[DavidC1]

It can still access it though? Why is the nomenclature L# is not applicable.

Levels suggest that it has to always go through it before main memory, or the next level. It is called system wide cache for a reason. Such a broad cache will also not be as performant as a dedicated cache.

 

[gdansk]

Levels suggest that it has to always go through it before main memory, or the next level. It is called system wide cache for a reason. Such a broad cache will also not be as performant as a dedicated cache.

So L4 is filled directly from memory and doesn't look in the last level cache first?

 

[invisible_city]

What are you smoking? Sunny Cove is 18% faster than Skylake and Golden Cove is 19% faster than Sunny.

Skymont is 38% faster than Gracemont. This is a blowout increase alone, but there's also a 68% FP increase coming from the straight up doubling of FP performance, which will benefit vast majority of applications from beginning of the FP era, without needing to recompile like AVX512.

Skymont's FP unit is more capable than Golden Cove in
-64-bit FP: Literally everything
-128-bit FP: Everything from Core 2
-256-bit FP: Somewhat worse.

Assuming Int/FP split of 65/35%, that's a 50% gain. In 2022 it was Raptor Lake with Gracemont, and Golden Cove enhanced, and Zen 4.

Taking my figures from this IPC comparison of Gracemont, which is thought to be around Skylake IPC and Golden Cove: https://www.techpowerup.com/298887/...n-4-and-golden-cove-spring-surprising-results. That being said, Intel has previously said Gracemont outperforms Skylake, which I forgot about.

You're right that Intel's stated IPC is 19% average over Cypress Cove, which is ~19% above Skylake, or around 35%. The numbers don't make sense, must be relying on different workloads for comparison.

 

[DavidC1]

Taking my figures from this IPC comparison of Gracemont, which is known to be around Skylake IPC and Golden Cove: https://www.techpowerup.com/298887/...n-4-and-golden-cove-spring-surprising-results

That being said, Intel has previously said Gracemont outperforms Skylake, which I forgot about.

You're right that Intel's stated IPC is 19% average over Cypress Cove

Back in Gracemont days, Intel said it was approximately like Skylake without giving explicit figures. We found out that the FP is substantially slower(66% advantage for Golden Cove, meaning Skylake is likely 20% or so faster), and even in Integer it wasn't fully up to par.

Now they are saying it'll outright outperform Raptor Cove.

 

[invisible_city]

So in Lunar Lake the cache structure for the P core is as follows:
L1 (48K),
L2 (192K),
L3 (2.5MB),
L4 (12MB),
L5 (8MB)

Is that right?

Intel has stated that while L5/SLC is accessible to p-cores, in practice hit p-cores don't need/use L5, and keep in mind that this is shared between NPU and e-cores. More useful to think of Lunar Lake as 2 subsystems, P-cores with L1 - 4, E-cores with l1-3

 

[invisible_city]

Back in Gracemont days, Intel said it was approximately like Skylake without giving explicit figures. We found out that the FP is substantially slower(66% advantage for Golden Cove, meaning Skylake is likely 20% or so faster), and even in Integer it wasn't fully up to par.

Now they are saying it'll outright outperform Raptor Cove.

My point is that the the uplift over non-LP gracemont must be on the order of 20% for int and 50% for fp in Specint, adroc's fud notwithstanding.

Forgot to mention that intel state's on average LP gracemont IPC is down only ~5% with non-LP.

 

[DavidC1]

Intel has stated that while L5/SLC is accessible to p-cores, in practice hit rate is low, and keep in mind that this is shared between NPU and e-cores. More useful to think of Lunar Lake as 2 subsystems, P-cores with L1 - 4, E-cores with l1-3

The idea is to put everything in the cache as much as possible. So without the system level cache, the caches are for the cores only. Now it has a dedicated one for all uncore and I/O. Sharing reduces performance and increases latency so all units sharing will be low performance*, but for saving power it'll do wonders.

 

[DavidC1]

My point is that the the uplift over non-LP gracemont must be on the order of 20% for int and 50% for fp in Specint, adroc's fud notwithstanding.

Gracemont is actually slightly slower than Skylake in Int and something like 20% slower in FP if we take 66% Golden Cove and divide by 19% and 18%.

If it's 2% faster than Raptor Cove it'll be about 30% in Int.

Thoughts on Darkmont and Arctic Wolf:
-Darkmont is basically a Tick with few % improvements
-Arctic Wolf is the big one again with roughly 30% for Integer.

 

[invisible_city]

Gracemont is actually slightly slower than Skylake in Int and something like 20% slower in FP if we take 66% Golden Cove and divide by 19% and 18%.

If it's 2% faster than Raptor Cove it'll be about 30% in Int.

Mental math: order 20%=~30%. Raptor Cove vs Gracemont INT IPC in that techpowerup article is around 6.8 for Raptor Cove vs 5.53 for Gracemont 13th gen, 23%. Anyway, splitting hairs. My only point is that Adroc is throwing down some red herring cap by focusing on the fact that the comparison Intel drew was to LP cores.

 

[DavidC1]

Lunar Lake does sound excellent. I had a feeling they could pull it off. I had a mixed feeling for both Lakefield and Meteorlake, though I always thought it was possible to do good in theory.

40% lower video playback power is 60% higher battery life. Now we're cooking.

 

[ondma]

Dnt worry 8+32 model should take care of zen 5 and zen6

Depends on the use case, that is if we ever even see 8+32.. Should be great for embarrassingly parallel workloads, but more E cores wont help for gaming. Personally, I would rather see more P cores than continued spamming of E cores. If they feel the need, AMD has already stated they could increase core counts too.

 

[invisible_city]

Lunar Lake does sound excellent. I had a feeling they could pull it off. I had a mixed feeling for both Lakefield and Meteorlake, though I always thought it was possible to do good in theory.

40% lower video playback power is 60% higher battery life. Now we're cooking.

Yeah, this is the first time I've felt like Intel is executing since the early aughts. Fairchild/Intel was an innovation powerhouse. The beancounters almost sank them. This is a return to form, and we're seeing just the beginning of it. This is Intel's 2003 Dothan moment.

 

[dullard]

Depends on the use case, that is if we ever even see 8+32.. Should be great for embarrassingly parallel workloads, but more E cores wont help for gaming. Personally, I would rather see more P cores than continued spamming of E cores. If they feel the need, AMD has already stated they could increase core counts too.

P cores do well when fed massive amounts of power. If you just keep adding P cores, then within a given power budget, each subsequent P core gets less and less power. Meaning, very soon you get P cores with not enough power to work well. It could actually perform worse in games unless you get a CPU with a pitiful base clock and a massive power hungry turbo clock--but only turbo for the right number of cores to match your game.

If power use and heat dissipation weren't issues, then your desire would be great. But, in a real world situation, no chip can follow your dream path.

An army can't just double the number of soldiers, but give them no more food and no more supplies than an army half its size requires, and expect this starving army to perform well.