Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[poke01]

Some variants, yes.

ok, wow. So Desktop is keeping it then?

 

[adroc_thurston]

So Desktop is keeping it then?

No.
Just server.
Remember, Intel doesn't really have separate DT core variants, it's client and server.

 

[poke01]

If Skymont actually performs like Raptor Cove then the E's will finally fulfill their promise.

So Lion Cove will include HT after all.

If Skymont can equal Raptor Cove IPC and runs at 4.6GHz and Lion Cove does 5.4GHz nT and achieves a 15% bump over Raptor Cove than ARL should do a little over 48,000 CB R23 MT.

Zen 15 based on AMD's charts should do about 45,000 in CB R23 MT.

Now on top of all that speculation we don't know if those clocks for ARL are "burning down the house" or achievable with moderate air cooling.

As it has been for the last few generations I think the top of the stack parts for AMD and Intel are once again going to be very comparable.

umm. ARL should beat Zen 5 easy
TBD. Desktop does not have SMT

 

[poke01]

This asus guy really drags the keynotes lol

 

[Saylick]

ASUS Johnny as enthusiastic as ever, I see... lol

 

[adroc_thurston]

TBD

LNC is 14% moar PPC over RWC, which in itself was a ~4% PPC regression over RPC laptop (that's with 1.25MB L2) and the latter itself was a wee bit slower than the DT one with 2MB L2.
tl;dr it's that funny situation where everyone loses and gets a good laugh.

 

[Gideon]

Chips and cheese Lion Cove detials up:

Intel’s Lion Cove Architecture Preview

Intel’s P-Core’s lineage can be traced all the way back to the P6 architecture that was originally found in the Pentium Pro.

chipsandcheese.com

 

[gdansk]

On the otherhand the P core doesn't look great. ~14% going from Intel 7 to N3E... and clock rates regress a bit?
And we're disappointed with Zen 5.
We need the mont team to save x64.

 

[adroc_thurston]

14% going from Intel 7 to N3E... and clock rates regress a bit?

That's 14% over RWC. Not RPC. Not the desktop one either.

 

[poke01]

Chips and cheese Lion Cove detials up:

Intel’s Lion Cove Architecture Preview

Intel’s P-Core’s lineage can be traced all the way back to the P6 architecture that was originally found in the Pentium Pro.

chipsandcheese.com

"This means that while Lunar Lake may not support Hyperthreading, other products like Arrow Lake or a hypothetical future server CPU that use future P-Cores could support Hyperthreading if the application can benefit from it."

I guess we waitr for Intel to confirm

 

[Saylick]

I think this is the point in the presentation where I turn off the TV and read the press slides instead...

 

[poke01]

I think this is the point in the presentation where I turn off the TV and read the press slides instead...

The only keynotes I semi-fully watch are Apple ones. Cause they have fluff but not like this partner boredom

 

[adroc_thurston]

Cause they have fluff but not like this partner boredom

do i have to poast that cringe econerd sustainability song that kills every braincell at once

 

[Saylick]

At some point after the dust settles, we're going to need a nice place to do a proper comparison of all these cores. Just super interesting to see how they stack up in PPA. Exciting times.

 

[adroc_thurston]

At some point after the dust settles, we're going to need a nice place to do a proper comparison of all these cores. Just super interesting to see how they stack up in PPA. Exciting times.

Yeah, shame we can't do Z4c versus SKT isonode.

 

[poke01]

do i have to poast that cringe econerd sustainability song that kills every braincell at once

the eco stuff annoys me as well.

 

[Saylick]

Yeah, shame we can't do Z4c versus SKT isonode.

None of the comparisons will be iso-node, but it doesn't mean we can't estimate it. The silver lining is that Skymont is on a TSMC node, whom publishes detailed scaling parameters between their own nodes. It mitigates at least that variable.

 

[adroc_thurston]

The silver lining is that Skymont is on a TSMC node, whom publishes detailed scaling parameters between their own nodes. It mitigates at least that variable.

Comparatively Z4c should have more SRAM in core due to xboxhueg opcache so SKT should have an area advantage, particularly on N3b.

 

[Henry swagger]

If Skymont actually performs like Raptor Cove then the E's will finally fulfill their promise.

So Lion Cove will include HT after all.

If Skymont can equal Raptor Cove IPC and runs at 4.6GHz and Lion Cove does 5.4GHz nT and achieves a 15% bump over Raptor Cove than ARL should do a little over 48,000 CB R23 MT.

Zen 15 based on AMD's charts should do about 45,000 in CB R23 MT.

Now on top of all that speculation we don't know if those clocks for ARL are "burning down the house" or achievable with moderate air cooling.

As it has been for the last few generations I think the top of the stack parts for AMD and Intel are once again going to be very comparable.

8+32 refresh will still come and increase the performance lead 😀

 

[gdansk]

🤔 Really don't know what to make of that. Looks like for embarassingly parallel workloads it comes down to Z5's all core boost and whether or not desktop Arrow Lake has SMT. Or if AVX-512 comes out to play.

But the team behind Skymont shows that x64 isn't dead. "Throw more decoders at it bro, maybe it'll keep scaling." And lo, it did (so far).

 

[controlflow]

LNL is going to rain pretty hard on the Snapdragon X and ARM parade. The main issue Intel has is Qualcomm shipping a few months earlier.

 

[Saylick]

Comparatively Z4c should have more SRAM in core due to xboxhueg opcache so SKT should have an area advantage, particularly on N3b.

I wasn't thinking about going super detailed with estimating what size Zen 4c would be if ported to TSMC N3b by breaking out the logic and SRAM components. Realistically, would have used TSMC's 1.35x higher density and called it a day.

But yeah, Zen has a disadvantage due to how much cache AMD likes to use with their cores. Meanwhile it's the reverse with Skymont and its lack of L3 (I think?).

🤔 Really don't know what to make of that. Looks like for embarassingly parallel workloads it comes down to Z5's all core boost and whether or not desktop Arrow Lake has SMT. Or if AVX-512 comes out to play.

But the team behind Skymont shows that x64 isn't dead. "Throw more decoders at it bro, maybe it'll keep scaling." And lo, it did (so far).

At some point I have to imagine all designs have to converge. If Pat promotes the Mont team and they scrap the P cores in favor of scaling up the E cores to hit higher PPA, I suspect the E cores will eventually hit a wall of diminishing returns that will make it basically on par with Zen 5. I'm specifically using Zen 5 in this example because it clearly has better PPA than Lion Cove imo.

 

[poke01]

https://twitter.com/x/status/1797830413739770357

Looks good. Now this is a true low power chip.

 

[majord]

Did he not even talk about Arrow lake or did I miss something ? (other than mentioning it before going on about Panther lake)

Guess I'll hit up the slides

 

[gdansk]

Anandtech has N3E for the compute tile - is that a typo?