Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[lightisgood]

It's not just the chiplet partitioning, though that's not ideal either. The universal consensus seems to be that the SoC die is a mess. They rushed it terribly, and lost a lot of the architects midway through. Maybe Chips and Cheese can tease out some of the details.

There are some good ideas and notable improvements in MTL, but there's a lot of bad mixed in.

Most important things are ramping Intel 4 (+ Foveros etc...) in this year and competing MTL with APU.
Any other things are'nt important at all.

 

[adroc_thurston]

Any other things are'nt important at all.

Yes they are Jesus Christ what.
Intel failing to make their own IOD work well is a bad-bad precedent.

 

[poke01]

So glad T

Yes they are Jesus Christ what.
Intel failing to make their own IOD work well is a bad-bad precedent.

Yes, I had my doubts whether Intel would regain node leadership but that looks very unlikely.

Good thing future products are dual sourced.

 

[deasd]

I've got very good reason to think ARL doesn't have SMT either, take that for what it's worth.

Although admittedly, for the longest time I did just think it was a typo.

Other than copy-pasting what Apple/Qualcomm did, I guess it's due to TSMC process is not performance but high-density optimized, which cause frequency scaling lower than Intel's process? So Intel decide to disable SMT on client just for higher frequency?

 

[adroc_thurston]

So Intel decide to disable SMT on client just for higher frequency?

The core just has no SMT, simple as.

Other than copy-pasting what Apple/Qualcomm did

They really-really want to be Apple, yes.

 

[TESKATLIPOKA]

@TESKATLIPOKA, remember how I said there was a detail that would throw off your LNL projections. Well feel like recalculating without SMT ?

I thought It was something which would increase performance, disabling HT(SMT) is decreasing MT performance unless the saved power from the missing HT is enough to power additional E-cores, but 4+4 probably won't be very fast in Cinebench R23 MT for example.

I made a new calculation based on my old calculation. I will keep the clocks, but increase IPC by 25% for P-core and 15% for E-core, of course reality will be different, this is just for illustration.
LNL P-core 5.2GHz: 123*1.25=154 points
LNL P-core 3.9GHz: 100*1.25=125 points
LNL E-core 3.9GHz: 70*1.15= 81 points
Alder Lake P-core 5.2GHz: 123 points
Alder Lake P-core 3.9GHz: 100 points
Alder Lake E-core 3.9GHz: 70 points
Alder Lake HT 5.2GHz: 38 points
Alder Lake HT 3.9GHz: 31 points

Threads in use	4P+4E Lunar Lake 3.9GHz for both P/E cores	2P+8E Alder Lake 3.9GHz for both P/E cores	4P+4E Lunar Lake 5.2GHz P-core 3.9GHz E-core	2P+8E Alder Lake 5.2GHz P-core 3.9GHz E-core
1	125 [+25%]	100	154 [+25%]	123
2	250 [+25%]	200	308 [+25%]	246
3	375 [+39%]	270	462 [+46%]	316
4	450 [+32%]	340	616 [+60%]	386
5	531 [+30%]	410	697 [+53%]	456
6	612 [+28%]	480	778 [+48%]	526
7	693 [+26%]	550	859 [+44%]	596
8	774 [+25%]	620	940 [+41%]	666
9	774 [+12%]	690	940 [+28%]	736
10	774 [+2%]	760	940 [+17%]	806
11	774	791 [+2%]	940 [+11%]	844
12	774	822 [+6%]	940 [+7%]	882

The missing HT could be felt at higher thread count.

 

[eek2121]

No.

You made me go dig this up 🤣.

Note that this is for HP libraries. HD libraries are higher, but typically not suitable for high performance chips. Numbers are theoretical for both companies. Hopefully I made no errors copy pasting on mobile.

Intel 7 = ~60MTr/mm2
Intel 4 = ~123MTr/mm2
Intel 3 = ~160MTr/mm2
TSMC N7 = ~65MTr/mm2
TSMC N5 = ~95MTr/mm2
TSMC N4 = ~115MTr/mm2
TSMC N3 = ~124MTr/mm2

Note that companies can (and do) customize parameters that change these numbers. AMD does this, for example.

I will try and link the sources later if I remember.

 

[SpudLobby]

No.

edit: rereading.

I think he might actually be right though. If Zen 5 for mobile is on N4P and Lunar Lake is on N3, ARL 20A, my thought had been the exact same, they’ll have a mobile process advantage.

Desktops I suspect AMD will go N3 and servers the same of some kind for 5C. But for mobile it’s shaking out to be Intel regaining a process advantage, no? I don’t know how long that will last and frankly it’s not a huge deal seeing as Intel will still have more competition than ever before, but still.

Apple of course will have been on N3 for a while by then and Qualcomm by early to mid 2025 (when I suspect LNL and maybe even ARL are actually available) might have a successor chip as well on N3 at least coming, pending lawsuit. Zen 6 won’t be tooo far off.

 

[SpudLobby]

You made me go dig this up 🤣.

Note that this is for HP libraries. HD libraries are higher, but typically not suitable for high performance chips. Numbers are theoretical for both companies. Hopefully I made no errors copy pasting on mobile.

Intel 7 = ~60MTr/mm2
Intel 4 = ~123MTr/mm2
Intel 3 = ~160MTr/mm2
TSMC N7 = ~65MTr/mm2
TSMC N5 = ~95MTr/mm2
TSMC N4 = ~115MTr/mm2
TSMC N3 = ~124MTr/mm2

Note that companies can (and do) customize parameters that change these numbers. AMD does this, for example.

I will try and link the sources later if I remember.

AMD doesn’t use HP libraries to the extent Intel does, who basically scrapped those dense cells entirely with Intel 10/7 and likewise Intel 4 doesn’t even have any.



AMD relaxes the density some definitely and certainly customize the transistor choices so I doubt average density is crazy far off from Intel with HP libraries in Meteor Lake, but this is always such a silly sleight of hand people play when posting Intel’s HP peak density and claiming automatic champion, ignoring the use of HD everywhere other than Intel’s crappy design teams or that Intel’s last HD library straight up failed and they scrapped it.

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

fuse.wikichip.org

Here was Zen 2 and I suspect Zen 3 and Zen 4 especially on mobile — followed up with a similar strategy.

I also again want to note yields count — Samsung shows that fairly well in a way beyond immediate catastrophic defects too — and TSMC entered quality HVM in 2020 with N5 and shipped *millions* of A14 SoCs or even M series SoCs.

This stuff is a [redacted] measuring contest on steroids, which is fine for academic purposes until we start getting to “who has the bestest process” with bad entailments and flawed premises along with total apathy towards _shipping_ working product.

 

[SpudLobby]

I acknowledge that ARL-S has a high probability of being on N3. I genuinely didn't know that was the case with LNL as well. I can't find it anywhere on the internet either.

Fair enough, appreciate it.

 

[SpudLobby]

I'm pretty sure that Intel on their backside power delivery article they've already confirmed 20A on Arrow Lake next year, unless they retracted that statement..

I think there’s a rumor about it on N3 but only for desktops which would make sense for frequency purposes since N3 would be matured. I don’t know that’ll happen though seeing as the market is just only so large for desktops and may not justify it.

 

[SpudLobby]

It's not just the chiplet partitioning, though that's not ideal either. The universal consensus seems to be that the SoC die is a mess. They rushed it terribly, and lost a lot of the architects midway through. Maybe Chips and Cheese can tease out some of the details.

There are some good ideas and notable improvements in MTL, but there's a lot of bad mixed in. LNL had the luxury to learn from some of that secondhand, and also much more relaxed requirements (e.g. all-in on TSMC, so no process worries).

Honestly I’d take their chiplet partitioning over AMD’s with the CPU split up, but they could probably do well to merge a few things e.g. maybe IO and SoC or all three and the GPU.


What’s the SoC rumor?

 

[SpudLobby]

The core just has no SMT, simple as.

They really-really want to be Apple, yes.

I’m all for it. AVX decision is questionable insofar as they promoted it and then backed out, but doing stuff like no SMT, a separate e core design, Lunar Lake as an ultramobile 4+4 chip, good stuff.

 

[SpudLobby]

What’s the main reason though in dropping SMT? I assume

Verification complexity
Design complexity
Security
Would rather save that 5-15% of area, not that it isn’t technically “worth it” for performance but that really varies, can also harm performance in some cases.

 

[SpudLobby]

It's inherent to Lion Cove, for better or worse. ARL will have the same restrictions as Lunar Lake.

Lol the reactions to this from Intel and AMD fans are going to be so, so good. Muh beloved SMT/HT.

 

[SpudLobby]

Oh man... The SMT4 guy would've been so sad... 😥

In retrospect (or not for me) I always thought it was hilarious people got so excited about strange BS like SMT4 as opposed to just throwing more e cores at the problem and a bigger ST “big” core to handle beefier out of order code. It’s obvious which way the wind has been blowing and somewhat clear why.

 

[igor_kavinski]

In retrospect (or not for me) I always thought it was hilarious people got so excited about strange BS like SMT4 as opposed to just throwing more e cores at the problem

But but but why can't the E-cores have SMT???? It's only 5% extra die space per E-core. Give them 50% larger cache and let's have DOUBLE the threads!

 

[SpudLobby]

But but but why can't the E-cores have SMT???? It's only 5% extra die space per E-core. Give them 50% larger cache and let's have DOUBLE the threads!!

It adds complexity in design and verification and the benefits aren’t invariably crazy at least relative to the die area. Also adds security concerns.

Finally it’s actually possible to hurt performance in some cases. Intel should focus more on great ST with efficient power consumption and strong concurrent performance with additional, area efficient (and/or power efficient) cores. The HT stuff is such a distraction imo.

 

[ondma]

I remain skeptical, but if ARL does in fact not have hyperthreading, how will that affect gaming? As far as I know games dont really use the e cores, but does gaming us the hyperthreaded "cores" on the P cores? Seems to me that loss of hyperthreading could be a big problem for gaming, and I though ARL was supposed to be a gaming focused architecture. Seems like eventually Intel is going to have to figure out how to offload gaming (at least some tasks of it) to the e cores if they are to remain competitive.

 

[H433x0n]

You made me go dig this up 🤣.

Note that this is for HP libraries. HD libraries are higher, but typically not suitable for high performance chips. Numbers are theoretical for both companies. Hopefully I made no errors copy pasting on mobile.

Intel 7 = ~60MTr/mm2
Intel 4 = ~123MTr/mm2
Intel 3 = ~160MTr/mm2
TSMC N7 = ~65MTr/mm2
TSMC N5 = ~95MTr/mm2
TSMC N4 = ~115MTr/mm2
TSMC N3 = ~124MTr/mm2

Note that companies can (and do) customize parameters that change these numbers. AMD does this, for example.

I will try and link the sources later if I remember.

Those numbers are a little off, GNR will not be 160Mtr/mm2 when you account for the whole die. Intel 3 would only hit 160Mtr/mm2 on a theoretical smaller compute tile like MTL for example.

The TSMC numbers (per angstronomics)
N5 HP Cell: 92.3 MT/mm²
N4 HP Cell: 97.8 MT/mm²
N3B HP Cell: 124.00 MT/mm² (N3E is slightly less)

This is only comparing HP cells though. The N3 HD cells probably have better density, leakage and yield that could give an advantage to low power devices compared to Intel 3.

 

[H433x0n]

AMD doesn’t use HP libraries to the extent Intel does, who basically scrapped those dense cells entirely with Intel 10/7 and likewise Intel 4 doesn’t even have any.



AMD relaxes the density some definitely and certainly customize the transistor choices so I doubt average density is crazy far off from Intel with HP libraries in Meteor Lake, but this is always such a silly sleight of hand people play when posting Intel’s HP peak density and claiming automatic champion, ignoring the use of HD everywhere other than Intel’s crappy design teams or that Intel’s last HD library straight up failed and they scrapped it.

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

fuse.wikichip.org

Here was Zen 2 and I suspect Zen 3 and Zen 4 especially on mobile — followed up with a similar strategy.

I also again want to note yields count — Samsung shows that fairly well in a way beyond immediate catastrophic defects too — and TSMC entered quality HVM in 2020 with N5 and shipped *millions* of A14 SoCs or even M series SoCs.

This stuff is a [redacted] measuring contest on steroids, which is fine for academic purposes until we start getting to “who has the bestest process” with bad entailments and flawed premises along with total apathy towards _shipping_ working product.

This is a really good take / counter argument.

I feel like this comes down to design philosophy and company history. Intel is not TSMC. Intel’s fabs never had much of a reason to be concerned with anything other than the HPC segment. They also never had the same incentives to achieve a D0 that would be comparable to a business like TSMC. Their fabs existed to produce Intel products, not necessarily produce industry leading margins or produce wafers to satisfy the requirements of companies like Apple.

I wouldn’t totally discount the the importance of HP libraries either though since it is the most important library for Intel going forward and it is a valid comparison since we’re comparing 3 & 4 fin libraries directly to each other. I also wouldn’t assume that TSMC’s advantage with certain segments of FinFet are eternal. The entire playing field is in the process of being reset with GAA & BPD.

 

[adroc_thurston]

but doing stuff like no SMT, a separate e core design, Lunar Lake as an ultramobile 4+4 chip, good stuff.

None of that is good lol.

at least relative to the die area

SMT doesn't cost any die area (more or less).
It's just more validation time.
Intel only killed it because Apple has no SMT.
That is the only reason.

 

[poke01]

I remain skeptical, but if ARL does in fact not have hyperthreading, how will that affect gaming? As far as I know games dont really use the e cores, but does gaming us the hyperthreaded "cores" on the P cores? Seems to me that loss of hyperthreading could be a big problem for gaming, and I though ARL was supposed to be a gaming focused architecture. Seems like eventually Intel is going to have to figure out how to offload gaming (at least some tasks of it) to the e cores if they are to remain competitive.

HT does not have an effect on gaming. Apples CPUs do not have them and yet they are very powerful for gaming.

 

[adroc_thurston]

Apples CPUs do not have them and yet they are very powerful for gaming.

No one really ever tested that properly since aa64-native games can be counted on a single hand and you can't really dGPU on Apple parts either.

 

[naukkis]

HT does not have an effect on gaming. Apples CPUs do not have them and yet they are very powerful for gaming.

HT does have effect on gaming. It makes games slower - some cases by big margin. For gaming HT is best turned off if there's enough cores without.