Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[S'renne]

Too vague for me to tell how much he/she knows, but @adroc_thurston is certainly right that LNL is by far the more interesting of the two.

Lunar Lake is and always was on N3.

As far as I'm aware, this is not true, though it's possible I'm behind the curve. I'd take that claim with quite a bit of salt, however.

I'm pretty sure that Intel on their backside power delivery article they've already confirmed 20A on Arrow Lake next year, unless they retracted that statement..

 

[poke01]

LNL is by far the more interesting of the two.

Any particular reason why?

 

[eek2121]

A properly balanced core won’t have the resources for SMT. If Intel is dropping SMT, perhaps they have rebalanced the whole core. If that is the case, things are going to get VERY interesting.

Widely rumored by now

Not by any credible source.

I acknowledge that ARL-S has a high probability of being on N3. I genuinely didn't know that was the case with LNL as well. I can't find it anywhere on the internet either.

Intel 4/3 > TSMC N5/N4/N3. It doesn’t matter if Intel 20a/18a is used for Arrow Lake/Lunar Lake or not, Intel will have a process advantage. AMD is using N5/N4 for Zen 5.

Intel has already stated that Intel 4/3 could be used if they run into problems with 20A/18A. IIRC This all goes back to the original Investor Day presentations.

 

[adroc_thurston]

that LNL is by far the more interesting of the two.

Was.
Was more interesting.

this is not true

It is true, 20A parts went MIA, 18A ones still seemingly intact.

A properly balanced core won’t have the resources for SMT

That's just not true.

 

[igor_kavinski]

Was.
Was more interesting.

Lost all faith in Intel, eh?

 

[lightisgood]

" Intel 3, Intel 20A, and Intel 18A remain on track", Intel announced in 1Q23 earnings report (This must not be a lie).

We should wait and see 2Q23 earnings report...

 

[clemsyn]

Was.
Was more interesting.

It is true, 20A parts went MIA, 18A ones still seemingly intact.

That's just not true.

Is it possible that they are bypassing 20A because 18A is turning out good for them?

 

[jpiniero]

Is it possible that they are bypassing 20A because 18A is turning out good for them?

More likely that the client tiles that were (at least talked about) on 20A are also dual sourced at TSMC. Intel must have decided that keeping the 20A version wasn't worth it.

The 18A server products are likely only on 18A. Intel may get to the point where they feel like they need to have the server products at TSMC to remain competitive... but obviously they would want to unload the fabs first before doing that.

 

[lightisgood]

Intel must have decided that keeping the 20A version wasn't worth it.

I would like to suggest an alternative situation.
here.

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Page 52 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[adroc_thurston]

Lost all faith in Intel, eh?

It's been a really disappointing half a year for that.

More likely that the client tiles that were (at least talked about) on 20A are also dual sourced at TSMC. Intel must have decided that keeping the 20A version wasn't worth it.

bingo

 

[dullard]

" Intel 3, Intel 20A, and Intel 18A remain on track", Intel announced in 1Q23 earnings report (This must not be a lie).

Those nodes could be on track and Intel still might not use them for their CPUs.

 

[dullard]

If I understand correctly, here is where Intel stands.

1) Intel has stated for over 4 years that they will try all options. All options means using their own nodes, backporting CPUs, and using external fabs. (red circles were my emphasis) https://images.anandtech.com/doci/15217/20190916 SPIE Photomask and EUVL Plenary - Phillips v23-VRL2 distribute-page-019.jpg



2) There is no financial reason for all options to make it to the market. Intel would use what is best for Intel at the time. Thus, many options would be canned.
3) Intel has publicly stated that all options include CPUs that could be using x86 tiles from other fabs. https://www.anandtech.com/show/1657...-on-intel-ip-blocks-for-foundry-cores-on-tsmc
4) Intel has stated that Arrow Lake will be on 20A and external. https://www.intel.com/content/www/u...ogy-roadmaps-milestones.html#client-computing
5) Same link as #4 says "Lunar Lake and Beyond – Fueled by its IDM 2.0 strategy, Intel will be using both internal and external process nodes to deliver leadership products."

Go back to item #1 above. Suppose all options work. Intel's node works, backporting could work, external fabs could work. Suppose Intel already bought the fab production. What would you do in that situation? Use the external fab or ditch that lost money and fab it yourself?

 

[Exist50]

Any particular reason why?

Very different SoC. Hopefully time to develop something better than MTL's garbage.

Was.
Was more interesting.

I'm not aware of any substantial recent development with LNL. Can you elaborate?

It is true, 20A parts went MIA, 18A ones still seemingly intact.

There've certainly been reports that they rejiggered which products the 20A die would go into. Sure that may not be the source of confusion?

 

[Exist50]

Intel 4/3 > TSMC N5/N4/N3. It doesn’t matter if Intel 20a/18a is used for Arrow Lake/Lunar Lake or not, Intel will have a process advantage.

No.

 

[A///]

Lulz. Zen 3 will have SMT4 despite all evidence to the contrary. AMD should release a "double 3600" cheaper than a 3800X. What a clown. Sad part is I don't think he was a troll.

Those were two different people actually but the point still stands.

mental illness plagues many countries and thusly many people.

 

[H433x0n]

Very different SoC. Hopefully time to develop something better than MTL's garbage.

You have a lot of good info and knowledge but then you say stuff like this and it throws me for a loop.

To me, ‘garbage’ is Rocket Lake, Kaby Lake, etc. MTL is on a new node, has new features and is the most advanced non monolithic client CPU Intel has done to date.

 

[adroc_thurston]

MTL is on a new node, has new features and is the most complex non monolithic client CPU Intel has done to date.

Doesn't make it good.
Just needlessly complex.

 

[lightisgood]

Doesn't make it good.
Just needlessly complex.

You might be in the moore's law living world.
But realworld is not.

Intel 4 displays good logic dense, however, memory (SRAM) dense is'nt so competitive.
So, MTL has ADM cache (probably ADM is eDRAM).
This is thanks to Foveros.

 

[ashFTW]

Doesn't make it good.
Just needlessly complex.

MTL has been designed with modularity so that presumably various chiplets can be ”plug and play” to create different products, but if that modularity is not exploited then it’s indeed needlessly complex.

 

[adroc_thurston]

You might be in the moore's law living world.
But realworld is not.

Tiny mobile parts are not really affected.

Intel 4 displays good logic dense, however, memory (SRAM) dense is'nt so competitive.
So, MTL has ADM cache (probably ADM is eDRAM).
This is thanks to Foveros.

Yes, it's needlessly complex.

MTL has been designed with modularity so that presumably various chiplets can be ”plug and play” to create different products

Ugh, nope, only SOC/IOE tiles get reused for ARL and neither have any relation to Lunar-onwards.

 

[H433x0n]

Doesn't make it good.
Just needlessly complex.

What’s the alternative, keeping it monolithic? That’s not really a step forward either. A chiplet design similar to Ryzen client desktop isn’t a viable alternative for the low power mobile segment.

What is it supposed to do to not be trash?

 

[lightisgood]

Ugh, nope, only SOC/IOE tiles get reused for ARL and neither have any relation to Lunar-onwards.

Tile arch has some advantage not only reusing IP but also flexible choosing process node, easy debugging, better yield and so on.

If MTL were monolithic, MTL could be a product in 2024.

You can study "why MTL is being MTL" from resource of Hot Chips 34.

 

[adroc_thurston]

What’s the alternative, keeping it monolithic?

Less tiles.

What is it supposed to do to not be trash?

Not be needlessly complex versus what came before.

If MTL were monolithic

Just do less tiles.
Adding packaging overhead where there should be none is silly.

 

[H433x0n]

Tile arch has some advantage not only reusing IP but also flexible choosing process node, easy debugging, better yield and so on.

If MTL were monolithic, MTL could be a product in 2024.

You can study "why MTL is being MTL" from resource of Hot Chips 34.

There’s also the process node aspect. to produce a single compute tile makes node transitions much easier.

Less tiles.

Not be needlessly complex versus what came before.

Just do less tiles.
Adding packaging overhead where there should be none is silly.

This seems like a distinction without a difference. You're proposing to combine the SoC and GPU tile? That makes it even less flexible and likely doesn't do much to reduce complexity.

 

[Exist50]

You have a lot of good info and knowledge but then you say stuff like this and it throws me for a loop.

To me, ‘garbage’ is Rocket Lake, Kaby Lake, etc. MTL is on a new node, has new features and is the most advanced non monolithic client CPU Intel has done to date.

It's not just the chiplet partitioning, though that's not ideal either. The universal consensus seems to be that the SoC die is a mess. They rushed it terribly, and lost a lot of the architects midway through. Maybe Chips and Cheese can tease out some of the details.

There are some good ideas and notable improvements in MTL, but there's a lot of bad mixed in. LNL had the luxury to learn from some of that secondhand, and also much more relaxed requirements (e.g. all-in on TSMC, so no process worries).